diff options
| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2020-11-10 10:25:04 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-02-24 11:27:51 +0000 |
| commit | 291b58f06e4d9472fa2b8b8ace5b7829fe625d45 (patch) | |
| tree | 11fa36a0866f6969f2a546a9892a3ca084b85655 /src/soc | |
| parent | aed1952f059baf71d5584b9a39ca31b3eebc7797 (diff) | |
| download | coreboot-291b58f06e4d9472fa2b8b8ace5b7829fe625d45.tar.xz | |
soc/intel/alderlake: Add soc_get_xhci_usb_info() for elog support
Add MMIO offsets for USB2 and USB3 port status registers, for
both north (TCSS) and south (PCH) XHCI controllers; implement
soc_get_xhci_usb_info() to return the appropriate entries for
elog.
Change-Id: I5ceb73707a0af0542a07027fd5c873a9658b19d6
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/alderlake/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/xhci.c | 44 |
2 files changed, 45 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/Makefile.inc b/src/soc/intel/alderlake/Makefile.inc index f31cf98dd7..fc3d63e0fa 100644 --- a/src/soc/intel/alderlake/Makefile.inc +++ b/src/soc/intel/alderlake/Makefile.inc @@ -45,6 +45,7 @@ ramstage-y += reset.c ramstage-y += smmrelocate.c ramstage-y += soundwire.c ramstage-y += systemagent.c +ramstage-y += xhci.c smm-y += gpio.c smm-y += p2sb.c diff --git a/src/soc/intel/alderlake/xhci.c b/src/soc/intel/alderlake/xhci.c new file mode 100644 index 0000000000..922633667f --- /dev/null +++ b/src/soc/intel/alderlake/xhci.c @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/pci_type.h> +#include <intelblocks/xhci.h> +#include <soc/pci_devs.h> + +/* + * Information obtained from Intel doc# 630094, ADL-P PCH EDS Vol. 2, + * as well as doc# 626817, ADL-P PCH EDS Vol. 1 + */ + +#define PCH_XHCI_USB2_PORT_STATUS_REG 0x480 +#define PCH_XHCI_USB3_PORT_STATUS_REG 0x540 +#define PCH_XHCI_USB2_PORT_NUM 10 +#define PCH_XHCI_USB3_PORT_NUM 4 + +#define TCSS_XHCI_USB2_PORT_STATUS_REG 0x480 +#define TCSS_XHCI_USB3_PORT_STATUS_REG 0x540 +#define TCSS_XHCI_USB2_PORT_NUM 10 +#define TCSS_XHCI_USB3_PORT_NUM 4 + +static const struct xhci_usb_info usb_info = { + .usb2_port_status_reg = PCH_XHCI_USB2_PORT_STATUS_REG, + .num_usb2_ports = PCH_XHCI_USB2_PORT_NUM, + .usb3_port_status_reg = PCH_XHCI_USB3_PORT_STATUS_REG, + .num_usb3_ports = PCH_XHCI_USB3_PORT_NUM, +}; + +static const struct xhci_usb_info tcss_usb_info = { + .usb2_port_status_reg = TCSS_XHCI_USB2_PORT_STATUS_REG, + .num_usb2_ports = TCSS_XHCI_USB2_PORT_NUM, + .usb3_port_status_reg = TCSS_XHCI_USB3_PORT_STATUS_REG, + .num_usb3_ports = TCSS_XHCI_USB3_PORT_NUM, +}; + +const struct xhci_usb_info *soc_get_xhci_usb_info(pci_devfn_t xhci_dev) +{ + if (xhci_dev == PCH_DEVFN_XHCI) + return &usb_info; + else if (xhci_dev == SA_DEVFN_TCSS_XHCI) + return &tcss_usb_info; + + return NULL; +} |