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authorIonela Voinescu <ionela.voinescu@imgtec.com>2015-01-26 13:29:34 +0000
committerPatrick Georgi <pgeorgi@google.com>2015-04-14 12:08:02 +0200
commit30fc6676dbfee43009b4110eb1ff7b4e03c91a37 (patch)
tree258e950d7aab484bd443d614c16d74fa20c24b27 /src/soc
parent55b8dc02e01c293f210af1bac3faaa7fdaae90c7 (diff)
downloadcoreboot-30fc6676dbfee43009b4110eb1ff7b4e03c91a37.tar.xz
pistachio: increase size of bootblock to 18 KB
With the added code for clock and MFIOs setup, bootblock now exceeds 16KB. This patch increases the allowed limit to 18KB. BUG=chrome-os-partner:31438 TEST=tested on Pistachio bring up board; works as expected BRANCH=none Change-Id: I166f882bd3db446bcd6f9e1f828cab22266c6ac7 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: da95db5ed348419b7905dc1ab68fd64d7b2eb5e0 Original-Change-Id: I0cacc6163f21ae3673c2716b12dde66bd48290f9 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/243213 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9665 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/imgtec/pistachio/include/soc/memlayout.ld6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
index 75387624cb..5b50a0a365 100644
--- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld
+++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
@@ -28,9 +28,9 @@ SECTIONS
/* GRAM becomes the SRAM. */
SRAM_START(0x9a000000)
- BOOTBLOCK(0x9a000000, 16K)
- ROMSTAGE(0x9a004000, 36K)
- CBFS_CACHE(0x9a00d000, 76K)
+ BOOTBLOCK(0x9a000000, 18K)
+ ROMSTAGE(0x9a004800, 36K)
+ CBFS_CACHE(0x9a00d800, 74K)
SRAM_END(0x9a020000)
/* Let's use SRAM for stack and CBMEM console. */