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authorAaron Durbin <adurbin@chromium.org>2016-07-18 00:35:42 -0500
committerAaron Durbin <adurbin@chromium.org>2016-07-19 20:18:08 +0200
commit32ac01823b8345ecd6f557a439153cc2a75596a9 (patch)
tree863aefacf526b521cb0438e1537cd1a7a709664a /src/soc
parentd04639b3d62dbd6a5fc7f48493411b9e74f990d1 (diff)
downloadcoreboot-32ac01823b8345ecd6f557a439153cc2a75596a9.tar.xz
drivers/intel/fsp2_0: load and relocate FSPS in cbmem
The FSPS component loading was just loading to any memory address listed in the header. That could be anywhere in the address space including ramstage itself -- let alone corrupting the OS memory on S3 resume. Remedy this by loading and relocating FSPS into cbmem. The UEFI 2.4 header files include path are selected to provide the types necessary for FSP relocation. BUG=chrome-os-partner:52679 Change-Id: Iaba103190731fc229566a3b0231cf967522040db Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15742 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: John Zhao <john.zhao@intel.com>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/apollolake/chip.c7
1 files changed, 1 insertions, 6 deletions
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index accc1bb1d0..3a6e90e5e2 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -25,7 +25,6 @@
#include <device/pci.h>
#include <fsp/api.h>
#include <fsp/util.h>
-#include <memrange.h>
#include <soc/iomap.h>
#include <soc/cpu.h>
#include <soc/intel/common/vbt.h>
@@ -192,7 +191,6 @@ static void pcie_override_devicetree_after_silicon_init(void)
static void soc_init(void *data)
{
- struct range_entry range;
struct global_nvs_t *gnvs;
/* Save VBT info and mapping */
@@ -203,10 +201,7 @@ static void soc_init(void *data)
* default policy that doesn't honor boards' requirements. */
itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
- /* TODO: tigten this resource range */
- /* TODO: fix for S3 resume, as this would corrupt OS memory */
- range_entry_init(&range, 0x200000, 4ULL*GiB, 0);
- fsp_silicon_init(&range);
+ fsp_silicon_init();
/* Restore GPIO IRQ polarities back to previous settings. */
itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);