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authorYen Lin <yelin@nvidia.com>2015-08-20 15:19:07 -0700
committerPatrick Georgi <pgeorgi@google.com>2015-08-28 06:45:31 +0000
commit3ad69e8d4c1270d037786d9f9fcb8c24ab6b267c (patch)
tree9f2710259825e898aa268b3b5e86488fdca50d88 /src/soc
parent3746465f4a6eede5acf2dcd9f9713de2c2663f3b (diff)
downloadcoreboot-3ad69e8d4c1270d037786d9f9fcb8c24ab6b267c.tar.xz
t210: sdram_lp0: also save EmcBctSpare2 field
Need to save EmcBctSpare2 field to scratch register. Without it, system may not resume from LP0 suspend. BUG=chrome-os-partner:43797 BRANCH=none TEST=able to suspend/resume >30 times on a known failed board Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: 6d1623c4c791f79e097193dfbc4bc894ef63e230 Original-Change-Id: I53ebf8c4d4c7cd19827128a84fbd97a377d78ff7 Original-Signed-off-by: Yen Lin <yelin@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/294765 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-(cherry picked from commit ce38d902e889068d0068150c9352c2ecdb2f8815) Original-Reviewed-on: https://chromium-review.googlesource.com/294864 Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Change-Id: I2ff21afbe9278413033101877c2581df51913709 Reviewed-on: http://review.coreboot.org/11401 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/nvidia/tegra210/sdram_lp0.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/nvidia/tegra210/sdram_lp0.c b/src/soc/nvidia/tegra210/sdram_lp0.c
index f3f2af3270..890c28544a 100644
--- a/src/soc/nvidia/tegra210/sdram_lp0.c
+++ b/src/soc/nvidia/tegra210/sdram_lp0.c
@@ -724,6 +724,7 @@ void sdram_lp0_save_params(const struct sdram_params *sdram)
s32(EmcBctSpare5, scratch42);
s32(EmcBctSpare4, scratch44);
s32(SwizzleRankByteEncode, scratch45);
+ s32(EmcBctSpare2, scratch46);
s32(EmcBctSpare1, scratch47);
s32(EmcBctSpare0, scratch48);
s32(EmcBctSpare9, scratch50);