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authorArthur Heymans <arthur@aheymans.xyz>2019-06-18 13:19:29 +0200
committerPatrick Georgi <pgeorgi@google.com>2019-06-21 08:59:15 +0000
commit4821a0e135ff2d60f552203d2724ae2d44850623 (patch)
treefbf6a703341fe1719b0d72f53d6da8f0d05ce5e2 /src/soc
parenta6a396ddb6f866c5a675dff5c1aa0b4cbaf44039 (diff)
downloadcoreboot-4821a0e135ff2d60f552203d2724ae2d44850623.tar.xz
soc/intel/cannonlake: Rename SOC_INTEL_COMMON_CANNONLAKE_BASE
What it really means to do is to use different FSP headers. Change-Id: I3c75d4aac8525ab2639608fb9c1b3a9afef0e943 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33575 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/cannonlake/Kconfig10
-rw-r--r--src/soc/intel/cannonlake/chip.h2
-rw-r--r--src/soc/intel/cannonlake/cpu.c2
-rw-r--r--src/soc/intel/cannonlake/romstage/fsp_params.c2
4 files changed, 8 insertions, 8 deletions
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index dac3522d0a..7b4282c934 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -3,7 +3,7 @@ config SOC_INTEL_CANNONLAKE
help
Intel Cannonlake support
-config SOC_INTEL_COMMON_CANNONLAKE_BASE
+config SOC_INTEL_CANNONLAKE_ALTERNATE_HEADERS
bool
default n
select SOC_INTEL_CANNONLAKE
@@ -11,7 +11,7 @@ config SOC_INTEL_COMMON_CANNONLAKE_BASE
Single Kconfig option to select common base Cannonlake support.
This Kconfig will help to select majority of CNL SoC features.
Major difference that exist today between
- SOC_INTEL_COMMON_CANNONLAKE_BASE and SOC_INTEL_CANNONLAKE Kconfig
+ SOC_INTEL_CANNONLAKE_ALTERNATE_HEADERS and SOC_INTEL_CANNONLAKE Kconfig
are in FSP Header Files. Hence this Kconfig might help to select
required SoC support FSP headers. Any future Intel SoC would
like to make use of CNL support might just select this Kconfig.
@@ -19,21 +19,21 @@ config SOC_INTEL_COMMON_CANNONLAKE_BASE
config SOC_INTEL_COFFEELAKE
bool
default n
- select SOC_INTEL_COMMON_CANNONLAKE_BASE
+ select SOC_INTEL_CANNONLAKE_ALTERNATE_HEADERS
help
Intel Coffeelake support
config SOC_INTEL_WHISKEYLAKE
bool
default n
- select SOC_INTEL_COMMON_CANNONLAKE_BASE
+ select SOC_INTEL_CANNONLAKE_ALTERNATE_HEADERS
help
Intel Whiskeylake support
config SOC_INTEL_COMETLAKE
bool
default n
- select SOC_INTEL_COMMON_CANNONLAKE_BASE
+ select SOC_INTEL_CANNONLAKE_ALTERNATE_HEADERS
help
Intel Cometlake support
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index 0d51c1ca5c..3b4c980e2d 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -111,7 +111,7 @@ struct soc_intel_cannonlake_config {
enum {
SaGv_Disabled,
SaGv_FixedLow,
-#if !CONFIG(SOC_INTEL_COMMON_CANNONLAKE_BASE)
+#if !CONFIG(SOC_INTEL_CANNONLAKE_ALTERNATE_HEADERS)
SaGv_FixedMid,
#endif
SaGv_FixedHigh,
diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c
index d98e2f5486..7dae615350 100644
--- a/src/soc/intel/cannonlake/cpu.c
+++ b/src/soc/intel/cannonlake/cpu.c
@@ -500,7 +500,7 @@ int soc_skip_ucode_update(u32 current_patch_id, u32 new_patch_id)
* have this check, where CNL CPU die is not based on KBL CPU
* so skip this check for CNL.
*/
- if (!CONFIG(SOC_INTEL_COMMON_CANNONLAKE_BASE))
+ if (!CONFIG(SOC_INTEL_CANNONLAKE_ALTERNATE_HEADERS))
return 0;
/*
diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c
index 77bad8f627..a1e3d76b4a 100644
--- a/src/soc/intel/cannonlake/romstage/fsp_params.c
+++ b/src/soc/intel/cannonlake/romstage/fsp_params.c
@@ -69,7 +69,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config)
/* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */
m_cfg->VmxEnable = CONFIG(ENABLE_VMX);
-#if CONFIG(SOC_INTEL_COMMON_CANNONLAKE_BASE)
+#if CONFIG(SOC_INTEL_CANNONLAKE_ALTERNATE_HEADERS)
m_cfg->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT;
#endif