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authorKyösti Mälkki <kyosti.malkki@gmail.com>2021-01-09 20:38:43 +0200
committerPatrick Georgi <pgeorgi@google.com>2021-02-09 07:52:31 +0000
commit4949a3dd626560aa504cee18d936d0d7602becfa (patch)
treeaa804caed95d613a0c9a1def5c44debfa22ef1ab /src/soc
parent1aaa72836d1a51b583b7a4352bceff72ab6ff091 (diff)
downloadcoreboot-4949a3dd626560aa504cee18d936d0d7602becfa.tar.xz
drivers/intel/fsp1_1,fsp2_0: Refactor logo display
Hide the detail of allocation from cbmem from the FSP. Loading of a BMP logo file from CBFS is not tied to FSP version and we do not need two copies of the code, move it under lib/. Change-Id: I909f2771af534993cf8ba99ff0acd0bbd2c78f04 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50359 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/apollolake/chip.c5
-rw-r--r--src/soc/intel/braswell/chip.c5
-rw-r--r--src/soc/intel/cannonlake/fsp_params.c5
-rw-r--r--src/soc/intel/skylake/chip.c5
4 files changed, 9 insertions, 11 deletions
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index 9670a31eba..39d9be5a84 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <acpi/acpi.h>
+#include <bootsplash.h>
#include <bootstate.h>
#include <cbmem.h>
#include <console/console.h>
@@ -850,9 +851,9 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *silconfig)
}
/* Handle FSP logo params */
-const struct cbmem_entry *soc_load_logo(FSPS_UPD *supd)
+void soc_load_logo(FSPS_UPD *supd)
{
- return fsp_load_logo(&supd->FspsConfig.LogoPtr, &supd->FspsConfig.LogoSize);
+ bmp_load_logo(&supd->FspsConfig.LogoPtr, &supd->FspsConfig.LogoSize);
}
BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, spi_flash_init_cb, NULL);
diff --git a/src/soc/intel/braswell/chip.c b/src/soc/intel/braswell/chip.c
index af274acdaa..e3c7aa850c 100644
--- a/src/soc/intel/braswell/chip.c
+++ b/src/soc/intel/braswell/chip.c
@@ -136,11 +136,6 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params)
board_silicon_USB2_override(params);
}
-const struct cbmem_entry *soc_load_logo(SILICON_INIT_UPD *params)
-{
- return fsp_load_logo(&params->PcdLogoPtr, &params->PcdLogoSize);
-}
-
void soc_display_silicon_init_params(const SILICON_INIT_UPD *old, SILICON_INIT_UPD *new)
{
/* Display the parameters for SiliconInit */
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index 075c3283cc..9d1d55fea5 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <bootsplash.h>
#include <cbmem.h>
#include <console/console.h>
#include <device/device.h>
@@ -589,7 +590,7 @@ const pci_devfn_t *soc_lpss_controllers_list(size_t *size)
}
/* Handle FSP logo params */
-const struct cbmem_entry *soc_load_logo(FSPS_UPD *supd)
+void soc_load_logo(FSPS_UPD *supd)
{
- return fsp_load_logo(&supd->FspsConfig.LogoPtr, &supd->FspsConfig.LogoSize);
+ bmp_load_logo(&supd->FspsConfig.LogoPtr, &supd->FspsConfig.LogoSize);
}
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index 88f432de01..cb0fa2a6b9 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <bootsplash.h>
#include <cbmem.h>
#include <fsp/api.h>
#include <acpi/acpi.h>
@@ -443,7 +444,7 @@ __weak void mainboard_silicon_init_params(FSP_S_CONFIG *params)
}
/* Handle FSP logo params */
-const struct cbmem_entry *soc_load_logo(FSPS_UPD *supd)
+void soc_load_logo(FSPS_UPD *supd)
{
- return fsp_load_logo(&supd->FspsConfig.LogoPtr, &supd->FspsConfig.LogoSize);
+ bmp_load_logo(&supd->FspsConfig.LogoPtr, &supd->FspsConfig.LogoSize);
}