diff options
| author | Aamir Bohra <aamir.bohra@intel.com> | 2019-12-09 16:05:52 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-02-04 16:14:50 +0000 |
| commit | 4d9d3f164de7002dd38f12dc40f9b260f63d2d9b (patch) | |
| tree | f49b32b7c994c45f73174f519791681f8c371927 /src/soc | |
| parent | d8663e0fc6629835eba44cc78e63e285aced897f (diff) | |
| download | coreboot-4d9d3f164de7002dd38f12dc40f9b260f63d2d9b.tar.xz | |
soc/intel/cannonlake: Allow Audio DSP OSC qualification for low power idle
With Audio DSP OSC qualification disabled from S0ix criteria.
S0ix is achieved before the DSP is suspended. When driver tries
to suspend DSP its already turned off.
BUG=b:139481313
Change-Id: I20b793b95483af03ce4ae068ac07864a9e90d39b
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37604
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/cannonlake/chip.h | 5 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/finalize.c | 9 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/include/soc/pmc.h | 3 |
3 files changed, 16 insertions, 1 deletions
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 0712146544..fd37d26492 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -59,8 +59,13 @@ struct soc_intel_cannonlake_config { uint32_t gen3_dec; uint32_t gen4_dec; + /* S0ix configuration */ + /* Enable S0iX support */ int s0ix_enable; + /* Enable Audio DSP oscillator qualification for S0ix */ + uint8_t cppmvric2_adsposcdis; + /* Enable DPTF support */ int dptf_enable; diff --git a/src/soc/intel/cannonlake/finalize.c b/src/soc/intel/cannonlake/finalize.c index 002e8ea42b..b2fb9f9ec6 100644 --- a/src/soc/intel/cannonlake/finalize.c +++ b/src/soc/intel/cannonlake/finalize.c @@ -91,11 +91,18 @@ static void pch_finalize(void) write8(pmcbase + PCH_PWRM_ACPI_TMR_CTL, reg8); } - /* Disable XTAL shutdown qualification for low power idle. */ if (config->s0ix_enable) { + /* Disable XTAL shutdown qualification for low power idle. */ reg32 = read32(pmcbase + CPPMVRIC); reg32 |= XTALSDQDIS; write32(pmcbase + CPPMVRIC, reg32); + + if (config->cppmvric2_adsposcdis) { + /* Enable Audio DSP OSC qualification for S0ix */ + reg32 = read32(pmcbase + CPPMVRIC2); + reg32 &= ~ADSPOSCDIS; + write32(pmcbase + CPPMVRIC2, reg32); + } } pch_handle_sideband(config); diff --git a/src/soc/intel/cannonlake/include/soc/pmc.h b/src/soc/intel/cannonlake/include/soc/pmc.h index 252c719925..fbd366bb2c 100644 --- a/src/soc/intel/cannonlake/include/soc/pmc.h +++ b/src/soc/intel/cannonlake/include/soc/pmc.h @@ -156,6 +156,9 @@ #define CPPMVRIC 0x1B1C #define XTALSDQDIS (1 << 22) +#define CPPMVRIC2 0x1B4C +#define ADSPOSCDIS (1 << 22) + #define IRQ_REG ACTL #define SCI_IRQ_ADJUST 0 #define ACTL 0x1BD8 |