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authorGabe Black <gabeblack@google.com>2014-05-06 15:33:37 -0700
committerMarc Jones <marc.jones@se-eng.com>2014-12-26 19:39:42 +0100
commit4dc3e28c741cd0b5ce6effeaec58eeda45b12303 (patch)
treeee931e10c47d9ea15fd6c4d5c384ede28b0721a0 /src/soc
parentc3101a09639062702707269cc59972d3f29c0652 (diff)
downloadcoreboot-4dc3e28c741cd0b5ce6effeaec58eeda45b12303.tar.xz
tegra124: Add a utility function to read the cause of the most recent reset.
When a watchdog reset happens, the SOC will reset but other parts of the system might not. In order to detect those situations we can check the rst_status register in the PMC. BUG=chrome-os-partner:28559 TEST=With this and a change which uses the new function in the nyan boards, built for nyan, nyan_big and nyan_blaze. Booted normally, through EC reset, software reset ("reboot" command from the terminal), and through watch dog reset. Verified that the new code only triggered during the watchdog reset and that the system rebooted and was able to boot without going into recovery mode unnecessarily. BRANCH=nyan Original-Change-Id: I7430768baa0304d4ec8524957a9cc37078ac5a71 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/198581 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Andrew Bresticker <abrestic@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 5fdc0239fc2960167dd9c074f3804bf9e4ad686a) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I5845d3a4d819868f5472c758e83e83b00e141b72 Reviewed-on: http://review.coreboot.org/7899 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/nvidia/tegra124/Makefile.inc1
-rw-r--r--src/soc/nvidia/tegra124/power.c5
-rw-r--r--src/soc/nvidia/tegra124/power.h11
3 files changed, 17 insertions, 0 deletions
diff --git a/src/soc/nvidia/tegra124/Makefile.inc b/src/soc/nvidia/tegra124/Makefile.inc
index fe66d43dbe..c7b2e16c4b 100644
--- a/src/soc/nvidia/tegra124/Makefile.inc
+++ b/src/soc/nvidia/tegra124/Makefile.inc
@@ -26,6 +26,7 @@ romstage-y += early_display.c
romstage-y += dma.c
romstage-y += i2c.c
romstage-y += monotonic_timer.c
+romstage-y += power.c
romstage-y += sdram.c
romstage-y += sdram_lp0.c
romstage-y += spi.c
diff --git a/src/soc/nvidia/tegra124/power.c b/src/soc/nvidia/tegra124/power.c
index a3cf5ef63b..760d058712 100644
--- a/src/soc/nvidia/tegra124/power.c
+++ b/src/soc/nvidia/tegra124/power.c
@@ -85,3 +85,8 @@ void power_ungate_cpu(void)
// Ungate power to CPU0 in the fast cluster.
power_ungate_partition(POWER_PARTID_CE0);
}
+
+int power_reset_status(void)
+{
+ return read32(&pmc->rst_status) & 0x7;
+}
diff --git a/src/soc/nvidia/tegra124/power.h b/src/soc/nvidia/tegra124/power.h
index 6454699a9c..130ed2525a 100644
--- a/src/soc/nvidia/tegra124/power.h
+++ b/src/soc/nvidia/tegra124/power.h
@@ -26,4 +26,15 @@ void power_enable_cpu_rail(void);
void power_ungate_cpu(void);
+// power_reset_status returns one of the following possible sources for the
+// most recent reset.
+enum {
+ POWER_RESET_POR = 0,
+ POWER_RESET_WATCHDOG = 1,
+ POWER_RESET_SENSOR = 2,
+ POWER_RESET_SW_MAIN = 3,
+ POWER_RESET_LP0 = 4
+};
+int power_reset_status(void);
+
#endif /* __SOC_NVIDIA_TEGRA124_POWER_H__ */