diff options
| author | Sugnan Prabhu S <sugnan.prabhu.s@intel.com> | 2021-03-18 22:08:22 +0530 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-04-22 15:59:25 +0000 |
| commit | 50f8b4ebdd7db8077b87ab7686637599c9d93af3 (patch) | |
| tree | e0ba2ff31243e54108ee8c0a44c27d7abf59447e /src/soc | |
| parent | c1c1ba5582fa0302476491c46f18cc73b69c88ac (diff) | |
| download | coreboot-50f8b4ebdd7db8077b87ab7686637599c9d93af3.tar.xz | |
soc/intel/alderlake: Add enum for HDA audio configuration
This change adds an enum to configure the audio related UPDs used for
configuring the audio over HDMI/DP and rename a variable for better
readability.
TEST=On shadowmountain audio sound cards are detected and listed by the
Linux kernel. Audio playback and capture is working fine.
Change-Id: I2834d6f4ce1651a609c5563af375f6e365d931fa
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/alderlake/chip.h | 19 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/romstage/fsp_params.c | 2 |
2 files changed, 17 insertions, 4 deletions
diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index e0d0b6074f..201150e8fc 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -113,9 +113,22 @@ struct soc_intel_alderlake_config { /* Audio related */ uint8_t PchHdaDspEnable; - uint8_t PchHdaIDispLinkTmode; - uint8_t PchHdaIDispLinkFrequency; - uint8_t PchHdaIDispCodecDisconnect; + + /* iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T */ + enum { + HDA_TMODE_2T = 0, + HDA_TMODE_4T = 2, + HDA_TMODE_8T = 3, + HDA_TMODE_16T = 4, + } PchHdaIDispLinkTmode; + + /* iDisp-Link Freq 4: 96MHz, 3: 48MHz. */ + enum { + HDA_LINKFREQ_48MHZ = 3, + HDA_LINKFREQ_96MHZ = 4, + } PchHdaIDispLinkFrequency; + + bool PchHdaIDispCodecEnable; struct pcie_rp_config pch_pcie_rp[CONFIG_MAX_PCH_ROOT_PORTS]; struct pcie_rp_config cpu_pcie_rp[CONFIG_MAX_CPU_ROOT_PORTS]; diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index 74d127ea98..9901354190 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -143,7 +143,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, memset(m_cfg->PchHdaAudioLinkSndwEnable, 0, sizeof(m_cfg->PchHdaAudioLinkSndwEnable)); m_cfg->PchHdaIDispLinkTmode = config->PchHdaIDispLinkTmode; m_cfg->PchHdaIDispLinkFrequency = config->PchHdaIDispLinkFrequency; - m_cfg->PchHdaIDispCodecDisconnect = config->PchHdaIDispCodecDisconnect; + m_cfg->PchHdaIDispCodecDisconnect = !config->PchHdaIDispCodecEnable; /* Disable all PCIe clock sources by default. And set RP irrelevant clock. */ for (i = 0; i < CONFIG_MAX_PCIE_CLOCK_SRC; i++) { |