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| author | Subrata Banik <subrata.banik@intel.com> | 2019-07-05 06:43:46 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2019-07-06 06:01:50 +0000 |
| commit | 5ee4c12ebb8ad82a62ab2325a9e972757534962e (patch) | |
| tree | cad17cc34a36d9f1a7b936ef52bf866eed6d1e8e /src/soc | |
| parent | 4f61f56be101d472990d631ab592f328117d5dbc (diff) | |
| download | coreboot-5ee4c12ebb8ad82a62ab2325a9e972757534962e.tar.xz | |
soc/intel/cannonlake: Override PRERAM_CBMEM_CONSOLE_SIZE default value
This patch increases PRERAM_CBMEM_CONSOLE_SIZE to fix
*** Pre-CBMEM romstage console overflowed, log truncated! ***
issue.
TEST=Verified on Hatch CML platform.
Change-Id: I2de4ca2f2001b304850c27df1b3c3b2c827fe25a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34006
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Spoorthi K
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/cannonlake/Kconfig | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index d697620725..5e405db4d8 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -326,4 +326,8 @@ config USE_LEGACY_8254_TIMER This sets the Enable8254ClockGating UPD, which according to the FSP Integration guide needs to be disabled in order to boot SeaBIOS, but should otherwise be enabled. +config PRERAM_CBMEM_CONSOLE_SIZE + hex + default 0xe00 + endif |