diff options
| author | Marc Jones <marcjones@sysproconsulting.com> | 2021-04-06 14:09:30 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-04-18 20:32:24 +0000 |
| commit | 64c6223759870286f9f344e0cd8663f582b3e0f1 (patch) | |
| tree | 4efc9222a64c43772b9f5ffdd7425adb0b7a4ec2 /src/soc | |
| parent | df40ca9d41ab1fcab3ddea3ce3c9aa95ab0da2b0 (diff) | |
| download | coreboot-64c6223759870286f9f344e0cd8663f582b3e0f1.tar.xz | |
soc/intel/xeon_sp: Set MSR locks
Set MSR locks as indicated by the Intel documents.
The following MSRs settings are locked:
MSR_FEATURE_CONFIG AES enable/disable lock
TURBO_ACTIVATION_RATIO_LOCK
This also adds PARALLEL_MP_AP_WORK to enable running on APs to set
each CPU MSR.
Change-Id: Iacf495f0880d42b378cb0d2c37940d50a511c430
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/xeon_sp/Kconfig | 1 | ||||
| -rw-r--r-- | src/soc/intel/xeon_sp/cpx/chip.c | 19 | ||||
| -rw-r--r-- | src/soc/intel/xeon_sp/include/soc/msr.h | 3 |
3 files changed, 23 insertions, 0 deletions
diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 61ab75090b..050511a5b0 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -36,6 +36,7 @@ config CPU_SPECIFIC_OPTIONS select POSTCAR_STAGE select IOAPIC select PARALLEL_MP + select PARALLEL_MP_AP_WORK select PMC_GLOBAL_RESET_ENABLE_LOCK select INTEL_DESCRIPTOR_MODE_CAPABLE select SOC_INTEL_COMMON_BLOCK diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c index 500f83e41a..34e0e27936 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.c +++ b/src/soc/intel/xeon_sp/cpx/chip.c @@ -4,6 +4,7 @@ #include <console/console.h> #include <console/debug.h> #include <cpu/x86/lapic.h> +#include <cpu/x86/mp.h> #include <device/pci.h> #include <intelblocks/acpi.h> #include <intelblocks/gpio.h> @@ -12,6 +13,7 @@ #include <soc/acpi.h> #include <soc/chip_common.h> #include <soc/cpu.h> +#include <soc/msr.h> #include <soc/pch.h> #include <soc/ramstage.h> #include <soc/p2sb.h> @@ -141,6 +143,22 @@ static void set_pcu_locks(void) } +static void set_msr_locks(void *unused) +{ + /* The MSRs and CSRS have the same register layout. Use the CSRS bit definitions */ + msr_t msr; + + /* Lock Turbo */ + msr = rdmsr(MSR_TURBO_ACTIVATION_RATIO); + msr.lo |= (TURBO_ACTIVATION_RATIO_LOCK); + wrmsr(MSR_TURBO_ACTIVATION_RATIO, msr); + + /* Lock AES enable */ + msr = rdmsr(MSR_FEATURE_CONFIG); + msr.lo |= FEATURE_CONFIG_LOCK; + wrmsr(MSR_FEATURE_CONFIG, msr); +} + static void chip_final(void *data) { /* Lock SBI */ @@ -157,6 +175,7 @@ static void chip_final(void *data) uint8_t reg8 = pci_io_read_config8(PCI_DEV(0, 0, 0), 0x88); pci_io_write_config8(PCI_DEV(0, 0, 0), 0x88, reg8 | (1 << 4)); + mp_run_on_all_cpus(set_msr_locks, NULL); set_pcu_locks(); p2sb_hide(); diff --git a/src/soc/intel/xeon_sp/include/soc/msr.h b/src/soc/intel/xeon_sp/include/soc/msr.h index dd05adc83f..3d68bf2565 100644 --- a/src/soc/intel/xeon_sp/include/soc/msr.h +++ b/src/soc/intel/xeon_sp/include/soc/msr.h @@ -5,6 +5,9 @@ #include <intelblocks/msr.h> +#define MSR_FEATURE_CONFIG 0x13c +#define FEATURE_CONFIG_LOCK BIT(0) + #define IA32_MCG_CAP 0x179 #define IA32_MCG_CAP_COUNT_MASK 0xff #define IA32_MCG_CAP_CTL_P_BIT 8 |