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authorMatt DeVillier <matt.devillier@gmail.com>2017-06-04 14:39:18 -0500
committerMartin Roth <martinroth@google.com>2018-03-07 21:19:10 +0000
commit687eb30dd869c43aeb1e2fc1964f520feb0f6d8e (patch)
tree140eb66367696e49cd36b08c15c5270e08a55989 /src/soc
parentdf2ae96ad8a83fb47d6cdff50353ad28b36ae87a (diff)
downloadcoreboot-687eb30dd869c43aeb1e2fc1964f520feb0f6d8e.tar.xz
soc/intel/braswell: add LPEA resources to southcluster.asl
The LPEA device memory resources, required by Windows drivers, were not being set. Allocate required resources per Inte'sl CHT Tianocore reference code. Test: boot Windows on google/edgar, observe LPEA device working properly. Change-Id: Ic3ecfc2ddade7d76dbaa95ffdd82599c3bcf35da Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/24987 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/braswell/acpi/southcluster.asl23
1 files changed, 23 insertions, 0 deletions
diff --git a/src/soc/intel/braswell/acpi/southcluster.asl b/src/soc/intel/braswell/acpi/southcluster.asl
index 19a58d119c..f7e3168126 100644
--- a/src/soc/intel/braswell/acpi/southcluster.asl
+++ b/src/soc/intel/braswell/acpi/southcluster.asl
@@ -153,6 +153,12 @@ Method (_CRS, 0, Serialized)
0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
0x00010000,,, FSEG)
+ /* LPEA Memory Region (0x20000000-0x201FFFFF) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x20000000, 0x201FFFFF, 0x00000000,
+ 0x00200000,,, LMEM)
+
/* PCI Memory Region (Top of memory-0xfeafffff) */
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
@@ -166,6 +172,23 @@ Method (_CRS, 0, Serialized)
0x00005000,,, TPMR)
})
+ /* Update LPEA resource area */
+ CreateDWordField (MCRS, LMEM._MIN, LMIN)
+ CreateDWordField (MCRS, LMEM._MAX, LMAX)
+ CreateDWordField (MCRS, LMEM._LEN, LLEN)
+ If (LAnd (LNotEqual (LPFW, Zero), LEqual (LPEN, One)))
+ {
+ Store (LPFW, LMIN)
+ Store (Add (LMIN, 0x001FFFFF), LMAX)
+ Store (0x00200000, LLEN)
+ }
+ Else
+ {
+ Store (Zero, LMIN)
+ Store (Zero, LMAX)
+ Store (Zero, LLEN)
+ }
+
/* Update PCI resource area */
CreateDwordField(MCRS, PMEM._MIN, PMIN)
CreateDwordField(MCRS, PMEM._MAX, PMAX)