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authorMichał Żygowski <michal.zygowski@3mdeb.com>2019-12-19 12:56:21 +0100
committerPatrick Georgi <pgeorgi@google.com>2019-12-20 17:54:42 +0000
commit727ac0d26395e4522e56ee988f1ef0097d982d51 (patch)
tree5961761c98afe3ee4851a3e92aa1679d77c0d0c8 /src/soc
parenta87a741b41ffb01612c7ef88d472d9092f707128 (diff)
downloadcoreboot-727ac0d26395e4522e56ee988f1ef0097d982d51.tar.xz
AMD {SoC, AGESA, binaryPI}: Don't use both of _ADR and _HID
PCI devices starting from 18 are processor configuration devices for each node and are not a bus itself. According to ACPI specification 6.3 section 6.1.5: "... _HID object must be used to describe any device that will be enumerated by OSPM. OSPM only enumerates a device when no bus enumerator can detect the device ID. ... Use the _ADR object to describe devices enumerated by bus enumerators other than OSPM." PCI device 18 with its functions has a standard enumerator, which is PCI enumerator so it needs a _ADR. Create a separate ACPI device for the processor configuration space. This fixes the ACPI compliance problem from CB:36318. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ie7b45ce8d9e4fdd80d90752bf51bba4d30041507 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37835 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/amd/picasso/acpi/northbridge.asl5
-rw-r--r--src/soc/amd/stoneyridge/acpi/northbridge.asl5
2 files changed, 8 insertions, 2 deletions
diff --git a/src/soc/amd/picasso/acpi/northbridge.asl b/src/soc/amd/picasso/acpi/northbridge.asl
index fe78534403..b1c2d31bc2 100644
--- a/src/soc/amd/picasso/acpi/northbridge.asl
+++ b/src/soc/amd/picasso/acpi/northbridge.asl
@@ -19,7 +19,6 @@ External (TOM1)
External (TOM2)
Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */
Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */
-Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */
/* Describe the Northbridge devices */
@@ -46,6 +45,10 @@ Device(AMRT) {
Name(_ADR, 0x00000000)
} /* end AMRT */
+Device(PCSD) { /* Processor configuration space devices */
+ Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */
+}
+
/* Internal Graphics */
Device(IGFX) {
Name(_ADR, 0x00010000)
diff --git a/src/soc/amd/stoneyridge/acpi/northbridge.asl b/src/soc/amd/stoneyridge/acpi/northbridge.asl
index fe78534403..b1c2d31bc2 100644
--- a/src/soc/amd/stoneyridge/acpi/northbridge.asl
+++ b/src/soc/amd/stoneyridge/acpi/northbridge.asl
@@ -19,7 +19,6 @@ External (TOM1)
External (TOM2)
Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */
Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */
-Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */
/* Describe the Northbridge devices */
@@ -46,6 +45,10 @@ Device(AMRT) {
Name(_ADR, 0x00000000)
} /* end AMRT */
+Device(PCSD) { /* Processor configuration space devices */
+ Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */
+}
+
/* Internal Graphics */
Device(IGFX) {
Name(_ADR, 0x00010000)