soc/intel/tigerlake: Add ACPI GPIO op

Add acpigen methods which generate operations to get/set/clear RX/TX GPIOs.
Verify it matches https://doc.coreboot.org/acpi/gpio.html.

BUG=b:149588766
TEST=confirmed with touchscreen gpios.

Signed-off-by: Alex Levin <levinale@chromium.org>
Change-Id: Id9fe26f14a606ceedb9db02d76fe8d466d3a21af
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40550
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Jes Klinke <jbk@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 37 insertions, 0 deletions

diff --git a/src/soc/intel/tigerlake/acpi.c b/src/soc/intel/tigerlake/acpi.c
index 36c488b575..f8d8986d77 100644
--- a/src/soc/intel/tigerlake/acpi.c
+++ b/src/soc/intel/tigerlake/acpi.c
@@ -330,3 +330,40 @@ int soc_madt_sci_irq_polarity(int sci)
 {
 	return MP_IRQ_POLARITY_HIGH;
 }
+
+static int acpigen_soc_gpio_op(const char *op, unsigned int gpio_num)
+{
+	/* op (gpio_num) */
+	acpigen_emit_namestring(op);
+	acpigen_write_integer(gpio_num);
+	return 0;
+}
+
+static int acpigen_soc_get_gpio_state(const char *op, unsigned int gpio_num)
+{
+	/* Store (op (gpio_num), Local0) */
+	acpigen_write_store();
+	acpigen_soc_gpio_op(op, gpio_num);
+	acpigen_emit_byte(LOCAL0_OP);
+	return 0;
+}
+
+int acpigen_soc_read_rx_gpio(unsigned int gpio_num)
+{
+	return acpigen_soc_get_gpio_state("\\_SB.PCI0.GRXS", gpio_num);
+}
+
+int acpigen_soc_get_tx_gpio(unsigned int gpio_num)
+{
+	return acpigen_soc_get_gpio_state("\\_SB.PCI0.GTXS", gpio_num);
+}
+
+int acpigen_soc_set_tx_gpio(unsigned int gpio_num)
+{
+	return acpigen_soc_gpio_op("\\_SB.PCI0.STXS", gpio_num);
+}
+
+int acpigen_soc_clear_tx_gpio(unsigned int gpio_num)
+{
+	return acpigen_soc_gpio_op("\\_SB.PCI0.CTXS", gpio_num);
+}