diff options
| author | Raul E Rangel <rrangel@chromium.org> | 2020-09-03 14:30:33 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-09-14 07:09:23 +0000 |
| commit | 7c79d8302b7361a11a204131d5661d768feb82ac (patch) | |
| tree | 8d233bf36810d7ea8af038e3b8317bb7dbff6e3e /src/soc | |
| parent | 73cd3e704fde61e287f6fbdd6d371ed19e41f15d (diff) | |
| download | coreboot-7c79d8302b7361a11a204131d5661d768feb82ac.tar.xz | |
soc/amd/picasso: Move sd_emmc_config into emmc_config struct
I plan on adding another eMMC parameter. This refactor keeps the config
contained in a single struct.
BUG=b:159823235
TEST=Build test
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I4b57d651ab44d6c1cad661d620bffd4207dfebd4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45095
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/amd/picasso/chip.h | 42 | ||||
| -rw-r--r-- | src/soc/amd/picasso/fsp_params.c | 2 |
2 files changed, 29 insertions, 15 deletions
diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h index ad492e0353..e3da2553b9 100644 --- a/src/soc/amd/picasso/chip.h +++ b/src/soc/amd/picasso/chip.h @@ -126,20 +126,34 @@ struct soc_amd_picasso_config { uint32_t telemetry_vddcr_soc_slope; uint32_t telemetry_vddcr_soc_offset; - enum { - SD_EMMC_DISABLE, - SD_EMMC_SD_LOW_SPEED, - SD_EMMC_SD_HIGH_SPEED, - SD_EMMC_SD_UHS_I_SDR_50, - SD_EMMC_SD_UHS_I_DDR_50, - SD_EMMC_SD_UHS_I_SDR_104, - SD_EMMC_EMMC_SDR_26, - SD_EMMC_EMMC_SDR_52, - SD_EMMC_EMMC_DDR_52, - SD_EMMC_EMMC_HS200, - SD_EMMC_EMMC_HS400, - SD_EMMC_EMMC_HS300, - } sd_emmc_config; + struct { + /* + * SDHCI doesn't directly support eMMC. There is an implicit mapping between + * eMMC timing modes and SDHCI UHS-I timing modes defined in the linux + * kernel. + * + * HS -> UHS_SDR12 (0x00) + * DDR52 -> UHS_DDR50 (0x04) + * HS200 -> UHS_SDR104 (0x03) + * HS400 -> NONE (0x05) + * + * The kernel driver uses a heuristic to determine if HS400 is supported. + */ + enum { + SD_EMMC_DISABLE, + SD_EMMC_SD_LOW_SPEED, + SD_EMMC_SD_HIGH_SPEED, + SD_EMMC_SD_UHS_I_SDR_50, + SD_EMMC_SD_UHS_I_DDR_50, + SD_EMMC_SD_UHS_I_SDR_104, + SD_EMMC_EMMC_SDR_26, + SD_EMMC_EMMC_SDR_52, + SD_EMMC_EMMC_DDR_52, + SD_EMMC_EMMC_HS200, + SD_EMMC_EMMC_HS400, + SD_EMMC_EMMC_HS300, + } timing; + } emmc_config; uint8_t xhci0_force_gen1; diff --git a/src/soc/amd/picasso/fsp_params.c b/src/soc/amd/picasso/fsp_params.c index f7f23b512e..b21f237c32 100644 --- a/src/soc/amd/picasso/fsp_params.c +++ b/src/soc/amd/picasso/fsp_params.c @@ -13,7 +13,7 @@ static void fsps_update_emmc_config(FSP_S_CONFIG *scfg, { int val = SD_DISABLE; - switch (cfg->sd_emmc_config) { + switch (cfg->emmc_config.timing) { case SD_EMMC_DISABLE: val = SD_DISABLE; break; |