summaryrefslogtreecommitdiff
path: root/src/soc
diff options
context:
space:
mode:
authorWim Vervoorn <wvervoorn@eltan.com>2020-03-30 12:17:54 +0200
committerPatrick Georgi <pgeorgi@google.com>2020-03-31 10:32:41 +0000
commit8602fb7f653ba127a3f6e3f277fc44143174feda (patch)
tree1e0d0dc5b1b07fbed586c2d36b2c8b586ecda98e /src/soc
parenteff1306ea480c991b7340928f67cbf59e6e11433 (diff)
downloadcoreboot-8602fb7f653ba127a3f6e3f277fc44143174feda.tar.xz
soc/intel/common/block/cse: Add check for CSE enabled
Exit print_me_fw_version if CSE is disabled. BUG=N/A TEST=tested on facebook monolith Change-Id: Ie3f1c2a5a7f96371a0da872efc3308850c382ba7 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39920 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/common/block/cse/cse.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c
index b93594aa50..86ed038b06 100644
--- a/src/soc/intel/common/block/cse/cse.c
+++ b/src/soc/intel/common/block/cse/cse.c
@@ -827,6 +827,10 @@ void print_me_fw_version(void *unused)
if (!CONFIG(CONSOLE_SERIAL))
return;
+ /* Ignore if CSE is disabled */
+ if (!is_cse_enabled())
+ return;
+
/*
* Ignore if ME Firmware SKU type is custom since
* print_boot_partition_info() logs RO(BP1) and RW(BP2) versions.