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authorFrans Hendriks <fhendriks@eltan.com>2019-06-18 12:18:55 +0200
committerMartin Roth <martinroth@google.com>2019-06-20 15:41:37 +0000
commit863853cd2d8e01db2045e73d96c502e4ecba8ad1 (patch)
treef3c64fa27ccce037ca5b47a45a41ae7014ba4083 /src/soc
parente48be35bca9a0656d1becb0c8a030a11eb8ffaa7 (diff)
downloadcoreboot-863853cd2d8e01db2045e73d96c502e4ecba8ad1.tar.xz
soc/intel/braswell/smbus.c: Add support for i2c mode block write
Intel Braswell supports i2c block write using SMBus controller. smbus_i2c_block_write() is added to configure SMBus controller in i2c mode before calling do_i2c_block_write(). Add smbus.c to ramstage. BUG=N/A TEST=Verify LCD display is working on Facebook FBG-1701 Change-Id: I50c1a03f624b3ab3b987d4f3b1d15dac4374e48a Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33225 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/braswell/Makefile.inc1
-rw-r--r--src/soc/intel/braswell/include/soc/smbus.h26
-rw-r--r--src/soc/intel/braswell/smbus.c32
3 files changed, 59 insertions, 0 deletions
diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc
index 1017d80c65..cc111da485 100644
--- a/src/soc/intel/braswell/Makefile.inc
+++ b/src/soc/intel/braswell/Makefile.inc
@@ -35,6 +35,7 @@ ramstage-$(CONFIG_ELOG) += elog.c
ramstage-y += emmc.c
ramstage-y += gpio.c
ramstage-y += gfx.c
+ramstage-y += smbus.c
ramstage-y += gpio_support.c
ramstage-y += iosf.c
diff --git a/src/soc/intel/braswell/include/soc/smbus.h b/src/soc/intel/braswell/include/soc/smbus.h
new file mode 100644
index 0000000000..8bc62f7eec
--- /dev/null
+++ b/src/soc/intel/braswell/include/soc/smbus.h
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
+ * Copyright (C) 2019 Eltan B.V.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_SMBUS_H_
+#define _SOC_SMBUS_H_
+
+/* PCI Configuration Space SMBus */
+#define HOSTC 0x40
+#define HOSTC_I2C_EN (1 << 2)
+
+int smbus_i2c_block_write(u8 addr, u8 bytes, u8 *buf);
+#endif /* _SOC_SMBUS_H_ */
diff --git a/src/soc/intel/braswell/smbus.c b/src/soc/intel/braswell/smbus.c
index 7e1b0dfbb0..1dfd4c7ecd 100644
--- a/src/soc/intel/braswell/smbus.c
+++ b/src/soc/intel/braswell/smbus.c
@@ -3,6 +3,7 @@
*
* Copyright (C) 2017 Intel Corporation.
* Copyright (C) 2019 3mdeb
+ * Copyright (C) 2019 Eltan B.V.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -16,6 +17,11 @@
#include <device/early_smbus.h>
#include <soc/iomap.h>
+#include <soc/pci_devs.h>
+#include <device/pci_def.h>
+#include <device/pci_type.h>
+#include <device/pci_ops.h>
+#include <soc/smbus.h>
#include <southbridge/intel/common/smbus.h>
u8 smbus_read_byte(u32 smbus_dev, u8 addr, u8 offset)
@@ -27,3 +33,29 @@ u8 smbus_write_byte(u32 smbus_dev, u8 addr, u8 offset, u8 value)
{
return do_smbus_write_byte(SMBUS_BASE_ADDRESS, addr, offset, value);
}
+
+int smbus_i2c_block_write(u8 addr, u8 bytes, u8 *buf)
+{
+#ifdef __SIMPLE_DEVICE__
+ pci_devfn_t dev = PCI_DEV(0, SMBUS_DEV, SMBUS_FUNC);
+#else
+ struct device *dev = pcidev_on_root(SMBUS_DEV, SMBUS_FUNC);
+#endif
+ u32 smbase;
+ u32 smb_ctrl_reg;
+ int status;
+
+ /* SMBus I/O BAR */
+ smbase = pci_read_config32(dev, PCI_BASE_ADDRESS_4) & 0xFFFFFFFE;
+
+ /* Enable I2C_EN bit in HOSTC register */
+ smb_ctrl_reg = pci_read_config32(dev, HOSTC);
+ pci_write_config32(dev, HOSTC, smb_ctrl_reg | HOSTC_I2C_EN);
+
+ status = do_i2c_block_write(smbase, addr, bytes, buf);
+
+ /* Restore I2C_EN bit */
+ pci_write_config32(dev, HOSTC, smb_ctrl_reg);
+
+ return status;
+}