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authorSubrata Banik <subrata.banik@intel.com>2018-11-19 16:23:01 +0530
committerNico Huber <nico.h@gmx.de>2018-11-19 19:42:06 +0000
commit87ca3898f90a24c92e8dffb70d617049b05d190c (patch)
treeb6c24cd4fd00a5417cac186ccfb58df214482fd9 /src/soc
parentc1fa44091e95451c592ac6f3852cf71cc490f429 (diff)
downloadcoreboot-87ca3898f90a24c92e8dffb70d617049b05d190c.tar.xz
soc/intel/{common, skylake}: Make ASPM enabling as common PCH feature
This patch moves required Kconfig selection for enabling ASPM feature (like clk_pm, L1 state etc) from soc code to intel common pch base code. TEST=Run lspci -vvv | grep ASPM The output shows the ASPM L1 is enable for pci devices Change-Id: Ic77602a75f0c9ccf28ebfd57e53433dc90985a16 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/29653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/common/block/pcie/Kconfig4
-rw-r--r--src/soc/intel/skylake/Kconfig4
2 files changed, 4 insertions, 4 deletions
diff --git a/src/soc/intel/common/block/pcie/Kconfig b/src/soc/intel/common/block/pcie/Kconfig
index c30d07e51e..aa32324401 100644
--- a/src/soc/intel/common/block/pcie/Kconfig
+++ b/src/soc/intel/common/block/pcie/Kconfig
@@ -1,5 +1,9 @@
config SOC_INTEL_COMMON_BLOCK_PCIE
bool
+ select PCIEXP_ASPM
+ select PCIEXP_CLK_PM
+ select PCIEXP_COMMON_CLOCK
+ select PCIEXP_L1_SUB_STATE
help
Intel Processor common PCIE support
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index ad5a754c1b..ae8253a53a 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -40,10 +40,6 @@ config CPU_SPECIFIC_OPTIONS
select NO_FIXED_XIP_ROM_SIZE
select PARALLEL_MP
select PARALLEL_MP_AP_WORK
- select PCIEXP_ASPM
- select PCIEXP_CLK_PM
- select PCIEXP_COMMON_CLOCK
- select PCIEXP_L1_SUB_STATE
select PCIEX_LENGTH_64MB
select REG_SCRIPT
select RTC