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| author | Michał Żygowski <michal.zygowski@3mdeb.com> | 2020-03-06 13:29:08 +0100 |
|---|---|---|
| committer | Michał Żygowski <michal.zygowski@3mdeb.com> | 2020-03-09 11:03:41 +0000 |
| commit | 915d1eaeae417b5e0114da33efe87272e3adb6e5 (patch) | |
| tree | 40e4eefbedd1fd46dc286ea23942d6ba84ad7f7e /src/soc | |
| parent | f8cd291344f2a8b8ecc90cfb7bb5ca864dcc9441 (diff) | |
| download | coreboot-915d1eaeae417b5e0114da33efe87272e3adb6e5.tar.xz | |
soc/intel/braswell/chip.h: Include smbios.h for Type9 Entries
In order to add the smbios_slot_desc for the SMBIOS Type9 entries into
the devicetree, and not use numbers but strings like
"SlotTypePciExpressGen3X4", smbios.h needs to be included in the
static.c.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Id15fe4101d14479b02e536fdf63748a241c02bd3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/braswell/chip.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h index 9f790dc140..ae9787b0a8 100644 --- a/src/soc/intel/braswell/chip.h +++ b/src/soc/intel/braswell/chip.h @@ -27,6 +27,7 @@ #include <fsp/util.h> #include <intelblocks/lpc_lib.h> #include <soc/pci_devs.h> +#include <smbios.h> #define SVID_CONFIG1 1 #define SVID_CONFIG3 3 |