soc/intel/xeon_sp: Clean up pci_devs.h

Prepare for merging cpx and skx pci_devs.h.

Remove duplicate defines. Move defines so they match each other.

Checked TiogaPass and DeltaLake BUILD_TIMELESS.

Change-Id: I146dd9e3f7eba053977d48dcf34d927dea310059
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45833
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

2 files changed, 57 insertions, 58 deletions

diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h
index 3781783935..965bb66088 100644
--- a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h
+++ b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h
@@ -71,21 +71,26 @@
 #define VTD_CAP_HIGH			0x0C
 #define VTD_EXT_CAP_HIGH		0x14
 
+/* CPU Devices */
+#define CBDMA_DEV_NUM           0x04
+
+#define VMD_DEV_NUM             0x05
+#define VMD_FUNC_NUM            0x05
+
+#define MMAP_VTD_CFG_REG_DEVID		0x2024
+#define VTD_DEV				0x5
+#define VTD_FUNC			0x0
+
+#define APIC_DEV_NUM            0x05
+#define APIC_FUNC_NUM           0x04
+
+
 /* PCH Device info */
 
 #define  XHCI_BUS_NUMBER        0x0
 #define  PCH_DEV_SLOT_XHCI      0x14
-#define   PCH_DEVFN_THERMAL	_PCH_DEVFN(XHCI, 2)
-
 #define  XHCI_FUNC_NUM          0x0
-
-#define HPET_BUS_NUM            0x0
-#define HPET_DEV_NUM            PCH_DEV_SLOT_LPC
-#define HPET0_FUNC_NUM          0x00
-
-#define MMAP_VTD_CFG_REG_DEVID		0x2024
-#define VTD_DEV				5
-#define VTD_FUNC			0
+#define   PCH_DEVFN_THERMAL	_PCH_DEVFN(XHCI, 2)
 
 #define PCH_DEV_SLOT_LPC        0x1f
 #define  PCH_DEVFN_LPC          _PCH_DEVFN(LPC, 0)
@@ -97,14 +102,9 @@
 #define  PCH_DEV_PMC            _PCH_DEV(LPC, 2)
 #define  PCH_DEV_SPI            _PCH_DEV(LPC, 5)
 
-#define CBDMA_DEV_NUM           0x04
-#define IIO_CBDMA_MMIO_SIZE     0x10000 //64kB for one CBDMA function
-
-#define VMD_DEV_NUM             0x05
-#define VMD_FUNC_NUM            0x05
-
-#define APIC_DEV_NUM            0x05
-#define APIC_FUNC_NUM           0x04
+#define HPET_BUS_NUM            0x0
+#define HPET_DEV_NUM            PCH_DEV_SLOT_LPC
+#define HPET0_FUNC_NUM          0x00
 
 #define PCH_IOAPIC_BUS_NUMBER   0x00
 #define PCH_IOAPIC_DEV_NUM      0x1F
diff --git a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h
index 62aa4d1e25..ab8537881b 100644
--- a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h
+++ b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h
@@ -31,10 +31,10 @@
 #define _PCH_DEV(slot, func)    PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func)
 #endif
 
-#define SAD_ALL_DEV                     29
-#define SAD_ALL_FUNC                    0
-#define SAD_ALL_PAM0123_CSR             0x40
-#define SAD_ALL_PAM456_CSR              0x44
+#define SAD_ALL_DEV			29
+#define SAD_ALL_FUNC			0
+#define SAD_ALL_PAM0123_CSR		0x40
+#define SAD_ALL_PAM456_CSR		0x44
 
 #define PCU_IIO_STACK                   1
 #define PCU_DEV                         30
@@ -54,45 +54,45 @@
 #define PCU_CR1_BIOS_MB_DATA_REG                           0x8c
 
 #define PCU_CR1_BIOS_MB_INTERFACE_REG                      0x90
-#define   BIOS_MB_RUN_BUSY_MASK                            ((uint32_t)1 << 31)
-#define   BIOS_MB_CMD_MASK                                 ((uint32_t)0xff)
+#define   BIOS_MB_RUN_BUSY_MASK                            BIT(31)
+#define   BIOS_MB_CMD_MASK                                 0xff
 #define   BIOS_CMD_READ_PCU_MISC_CFG                       0x5
 #define   BIOS_CMD_WRITE_PCU_MISC_CFG                      0x6
 #define   BIOS_ERR_INVALID_CMD                             0x01
 
 #define PCU_CR1_BIOS_RESET_CPL_REG                         0x94
-#define   RST_CPL1_MASK                                    ((uint32_t)1 << 1)
-#define   RST_CPL2_MASK                                    ((uint32_t)1 << 2)
-#define   RST_CPL3_MASK                                    ((uint32_t)1 << 3)
-#define   RST_CPL4_MASK                                    ((uint32_t)1 << 4)
-#define   PCODE_INIT_DONE1_MASK                            ((uint32_t)1 << 9)
-#define   PCODE_INIT_DONE2_MASK                            ((uint32_t)1 << 10)
-#define   PCODE_INIT_DONE3_MASK                            ((uint32_t)1 << 11)
-#define   PCODE_INIT_DONE4_MASK                            ((uint32_t)1 << 12)
+#define   RST_CPL1_MASK                                    BIT(1)
+#define   RST_CPL2_MASK                                    BIT(2)
+#define   RST_CPL3_MASK                                    BIT(3)
+#define   RST_CPL4_MASK                                    BIT(4)
+#define   PCODE_INIT_DONE1_MASK                            BIT(9)
+#define   PCODE_INIT_DONE2_MASK                            BIT(10)
+#define   PCODE_INIT_DONE3_MASK                            BIT(11)
+#define   PCODE_INIT_DONE4_MASK                            BIT(12)
 
 #define PCU_CR1_DESIRED_CORES_CFG2_REG                     0xa0
-#define PCU_CR1_DESIRED_CORES_CFG2_REG_LOCK_MASK           ((uint32_t)1 << 31)
-
-#define UBOX_DECS_BUS                                      0
-#define UBOX_DECS_DEV                                      8
-#define UBOX_DECS_FUNC                                     2
-#define UBOX_DECS_CPUBUSNO_CSR                             0xcc
-
-#define VTD_TOLM_CSR                    0xd0
-#define VTD_TSEG_BASE_CSR               0xa8
-#define VTD_TSEG_LIMIT_CSR              0xac
-#define VTD_EXT_CAP_LOW                 0x10
-#define VTD_MMCFG_BASE_CSR              0x90
-#define VTD_MMCFG_LIMIT_CSR             0x98
-#define VTD_TOHM_CSR                    0xd4
-#define VTD_MMIOL_CSR                   0xdc
-#define VTD_ME_BASE_CSR                 0xf0
-#define VTD_ME_LIMIT_CSR                0xf8
-#define VTD_VERSION                     0x00
-#define VTD_CAP                         0x08
-#define VTD_CAP_LOW                     0x08
-#define VTD_CAP_HIGH                    0x0C
-#define VTD_EXT_CAP_HIGH                0x14
+#define PCU_CR1_DESIRED_CORES_CFG2_REG_LOCK_MASK           BIT(31)
+
+#define UBOX_DECS_BUS			0
+#define UBOX_DECS_DEV			8
+#define UBOX_DECS_FUNC			2
+#define UBOX_DECS_CPUBUSNO_CSR		0xcc
+
+#define VTD_TOLM_CSR			0xd0
+#define VTD_TSEG_BASE_CSR		0xa8
+#define VTD_TSEG_LIMIT_CSR		0xac
+#define VTD_EXT_CAP_LOW			0x10
+#define VTD_MMCFG_BASE_CSR		0x90
+#define VTD_MMCFG_LIMIT_CSR		0x98
+#define VTD_TOHM_CSR			0xd4
+#define VTD_MMIOL_CSR			0xdc
+#define VTD_ME_BASE_CSR			0xf0
+#define VTD_ME_LIMIT_CSR		0xf8
+#define VTD_VERSION			0x00
+#define VTD_CAP				0x08
+#define VTD_CAP_LOW			0x08
+#define VTD_CAP_HIGH			0x0C
+#define VTD_EXT_CAP_HIGH		0x14
 
 #define PCU_CR1_C2C3TT_REG                                 0xdc
 #define PCU_CR1_PCIE_ILTR_OVRD                             0xfc
@@ -126,9 +126,9 @@
 #define HPET_DEV_NUM            PCH_DEV_SLOT_LPC
 #define HPET0_FUNC_NUM          0x00
 
-#define MMAP_VTD_CFG_REG_DEVID          0x2024
-#define VTD_DEV                         5
-#define VTD_FUNC                        0
+#define MMAP_VTD_CFG_REG_DEVID		0x2024
+#define VTD_DEV				5
+#define VTD_FUNC			0
 
 #define PCH_DEV_SLOT_LPC        0x1f
 #define  PCH_DEVFN_LPC          _PCH_DEVFN(LPC, 0)
@@ -140,7 +140,6 @@
 #define  PCH_DEV_PMC            _PCH_DEV(LPC, 2)
 #define  PCH_DEV_SPI            _PCH_DEV(LPC, 5)
 
-
 #define CBDMA_DEV_NUM           0x04
 #define IIO_CBDMA_MMIO_SIZE     0x10000 //64kB for one CBDMA function
 #define IIO_CBDMA_MMIO_ALIGNMENT 14 //2^14 - 16kB