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authorKyösti Mälkki <kyosti.malkki@gmail.com>2017-07-30 13:47:06 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2017-08-07 12:34:54 +0000
commitab1d2ac626d0535191b5f612707ae8f22c46c538 (patch)
tree695c3a34cc41702a1da8a9ebe2eb79f235c718bb /src/soc
parentd4ce1ded0174c2f2866e57023a68c6854f78e8a1 (diff)
downloadcoreboot-ab1d2ac626d0535191b5f612707ae8f22c46c538.tar.xz
usbdebug: Remove redundant setup
Taking ownership is handled with DBGP_OWNER within usbdebug driver code. Change-Id: Ia5da10d385cda1b4968f812967ea8a54d7e3c974 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20824 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Guckian <david.guckian@intel.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/broadwell/Kconfig4
-rw-r--r--src/soc/intel/broadwell/usb_debug.c7
2 files changed, 0 insertions, 11 deletions
diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig
index 51322012d0..9d6f978a67 100644
--- a/src/soc/intel/broadwell/Kconfig
+++ b/src/soc/intel/broadwell/Kconfig
@@ -185,10 +185,6 @@ config EHCI_BAR
hex
default 0xd8000000
-config EHCI_DEBUG_OFFSET
- hex
- default 0xa0
-
config SERIRQ_CONTINUOUS_MODE
bool
default y
diff --git a/src/soc/intel/broadwell/usb_debug.c b/src/soc/intel/broadwell/usb_debug.c
index fffebf00c6..683b4cc522 100644
--- a/src/soc/intel/broadwell/usb_debug.c
+++ b/src/soc/intel/broadwell/usb_debug.c
@@ -41,8 +41,6 @@ void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base)
{
- u32 tmp32;
-
if (!dev)
return;
@@ -51,9 +49,4 @@ void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base)
/* Enable access to the EHCI memory space registers. */
pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
-
- /* Force ownership of hte Debug Port to the EHCI controller. */
- tmp32 = read32((void *)(base + CONFIG_EHCI_DEBUG_OFFSET));
- tmp32 |= (1 << 30);
- write32((void *)(base + CONFIG_EHCI_DEBUG_OFFSET), tmp32);
}