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authorJagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com>2016-07-25 13:59:44 -0700
committerAaron Durbin <adurbin@chromium.org>2016-08-04 16:13:34 +0200
commitb6739d1b5666267a1c536bf8635e174436b836ae (patch)
treeed555f54b7004710d43a0e6cc6e3f490e7b91762 /src/soc
parentfec95be8b6e222ce73890577c0ecd32793d0df43 (diff)
downloadcoreboot-b6739d1b5666267a1c536bf8635e174436b836ae.tar.xz
soc/intel/apollolake: Configure gpio ownership
For the gpio based irq to work, the ownership of the pad should be changed to GPIO_DRIVER. Provide an option in the gpio defs to configure the PAD onwership. BUG=chrome-os-partner:54371 TEST=none Change-Id: I26d242d25d2034049340adf526045308fcdebbc0 Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Reviewed-on: https://review.coreboot.org/15871 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/apollolake/gpio.c23
-rw-r--r--src/soc/intel/apollolake/include/soc/gpio.h8
-rw-r--r--src/soc/intel/apollolake/include/soc/gpio_defs.h11
3 files changed, 42 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/gpio.c b/src/soc/intel/apollolake/gpio.c
index 2d325255e7..8ac00cde36 100644
--- a/src/soc/intel/apollolake/gpio.c
+++ b/src/soc/intel/apollolake/gpio.c
@@ -83,6 +83,27 @@ static void gpio_configure_itss(const struct pad_config *cfg,
itss_set_irq_polarity(irq, !!(cfg->config0 & PAD_CFG0_RX_POL_INVERT));
}
+static void gpio_configure_owner(const struct pad_config *cfg,
+ uint16_t port, int pin)
+{
+ uint32_t val;
+ uint16_t hostsw_reg;
+
+ /* The 4th bit in pad_config 1 (RO) is used to indicate if the pad
+ * needs GPIO driver ownership.
+ */
+ if (!(cfg->config1 & PAD_CFG1_GPIO_DRIVER))
+ return;
+
+ /* Based on the gpio pin number configure the corresponding bit in
+ * HOSTSW_OWN register. Value of 0x1 indicates GPIO Driver onwership.
+ */
+ hostsw_reg = HOSTSW_OWN_REG_BASE + ((pin / 32) * sizeof(uint32_t));
+ val = iosf_read(port, hostsw_reg);
+ val |= 1 << (pin % 32);
+ iosf_write(port, hostsw_reg, val);
+}
+
void gpio_configure_pad(const struct pad_config *cfg)
{
uint32_t dw1;
@@ -100,6 +121,8 @@ void gpio_configure_pad(const struct pad_config *cfg)
iosf_write(comm->port, config_offset + sizeof(uint32_t), dw1);
gpio_configure_itss(cfg, comm->port, config_offset);
+ gpio_configure_owner(cfg, comm->port, cfg->pad - comm->first_pad);
+
}
void gpio_configure_pads(const struct pad_config *cfg, size_t num_pads)
diff --git a/src/soc/intel/apollolake/include/soc/gpio.h b/src/soc/intel/apollolake/include/soc/gpio.h
index fc2401d165..8ef74bb70a 100644
--- a/src/soc/intel/apollolake/include/soc/gpio.h
+++ b/src/soc/intel/apollolake/include/soc/gpio.h
@@ -63,6 +63,14 @@ typedef uint32_t gpio_t;
PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \
PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE))
+/* General purpose input. The following macro sets the
+ * Host Software Pad Ownership to GPIO Driver mode.
+ */
+#define PAD_CFG_GPI_GPIO_DRIVER(pad, pull, rst) \
+ _PAD_CFG_STRUCT(pad, \
+ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \
+ PAD_PULL(pull) | PAD_CFG1_GPIO_DRIVER | PAD_IOSSTATE(TxLASTRxE))
+
/* No Connect configuration for unused pad.
* NC should be GPI with Term as PU20K, PD20K, NONE depending upon default Term
*/
diff --git a/src/soc/intel/apollolake/include/soc/gpio_defs.h b/src/soc/intel/apollolake/include/soc/gpio_defs.h
index 0a9fb151ea..d85f844823 100644
--- a/src/soc/intel/apollolake/include/soc/gpio_defs.h
+++ b/src/soc/intel/apollolake/include/soc/gpio_defs.h
@@ -45,6 +45,12 @@
#define MISCCFG_GPE0_DW2_SHIFT 16
#define MISCCFG_GPE0_DW2_MASK (0xf << MISCCFG_GPE0_DW2_SHIFT)
+/* Host Software Pad Ownership Register.
+ * The pins in the community are divided into 3 groups :
+ * GPIO 0 ~ 31, GPIO 32 ~ 63, GPIO 64 ~ 95
+ */
+#define HOSTSW_OWN_REG_BASE 0x80
+
#define PAD_CFG0_TX_STATE (1 << 0)
#define PAD_CFG0_RX_STATE (1 << 1)
#define PAD_CFG0_TX_DISABLE (1 << 8)
@@ -75,6 +81,11 @@
#define PAD_CFG0_RESET_PLTRST (2 << 30)
#define PAD_CFG0_RESET_RSMRST (3 << 30)
+/* Use the fourth bit in IntSel field to indicate gpio
+ * ownership. This field is RO and hence not used during
+ * gpio configuration.
+ */
+#define PAD_CFG1_GPIO_DRIVER (0x1 << 4)
#define PAD_CFG1_IRQ_MASK (0xff << 0)
#define PAD_CFG1_PULL_MASK (0xf << 10)
#define PAD_CFG1_PULL_NONE (0x0 << 10)