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authorAaron Durbin <adurbin@chromium.org>2014-09-23 16:33:21 -0500
committerPatrick Georgi <pgeorgi@google.com>2015-03-21 17:01:12 +0100
commitb9894efb86fd8b37aabaaea5bd19bac47c1438f0 (patch)
treec5871383609fd0877011215a29dfa0b4606c1f22 /src/soc
parent43933466e74dbdeb38ba8f5882ae8ed2372e3e4b (diff)
downloadcoreboot-b9894efb86fd8b37aabaaea5bd19bac47c1438f0.tar.xz
tegra132: convert to stopwatch API
Simplify the timed operations by using the stopwatch API. BUG=None BRANCH=None TEST=Built and booted to kernel. Analyzed logs. Output as expected. Change-Id: Ia49bccccc412f23bb620ed386b9174468a434116 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a877020c6d8ba12422c9c2c487122b7eb4a1967b Original-Change-Id: Iffc32fcb9b8bfdcfbef67f563ac3014912f82e7f Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/219494 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8831 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/nvidia/tegra132/ccplex.c25
-rw-r--r--src/soc/nvidia/tegra132/spi.c8
-rw-r--r--src/soc/nvidia/tegra132/timer.c18
3 files changed, 23 insertions, 28 deletions
diff --git a/src/soc/nvidia/tegra132/ccplex.c b/src/soc/nvidia/tegra132/ccplex.c
index 9f857070e0..90818b5515 100644
--- a/src/soc/nvidia/tegra132/ccplex.c
+++ b/src/soc/nvidia/tegra132/ccplex.c
@@ -38,9 +38,8 @@
static int ccplex_start(void)
{
- struct mono_time t1, t2;
- const long timeout_us = 1500000;
- long wait_time;
+ struct stopwatch sw;
+ const long timeout_ms = 1500;
const uint32_t handshake_mask = 1;
const uint32_t cxreset1_mask = 1 << 21;
uint32_t reg;
@@ -55,24 +54,22 @@ static int ccplex_start(void)
reg |= cxreset1_mask;
write32(reg, &clk_rst->rst_cpu_cmplx_set);
- timer_monotonic_get(&t1);
+ stopwatch_init_msecs_expire(&sw, timeout_ms);
while (1) {
reg = read32(&pmc->scratch118);
- timer_monotonic_get(&t2);
-
- wait_time = mono_time_diff_microseconds(&t1, &t2);
/* Wait for the bit to be knocked down. */
if ((reg & handshake_mask) != handshake_mask)
break;
- if (wait_time >= timeout_us) {
+ if (stopwatch_expired(&sw)) {
printk(BIOS_DEBUG, "MTS handshake timeout.\n");
return -1;
}
}
- printk(BIOS_DEBUG, "MTS handshake took %ld us.\n", wait_time);
+ printk(BIOS_DEBUG, "MTS handshake took %ld us.\n",
+ stopwatch_duration_usecs(&sw));
return 0;
}
@@ -140,7 +137,7 @@ static void request_ram_repair(void)
const uint32_t req = 1 << 0;
const uint32_t sts = 1 << 1;
uint32_t reg;
- struct mono_time t1, t2;
+ struct stopwatch sw;
printk(BIOS_DEBUG, "Requesting RAM repair.\n");
@@ -148,12 +145,12 @@ static void request_ram_repair(void)
reg |= req;
write32(reg, &flow->ram_repair);
- timer_monotonic_get(&t1);
- while ((read32(&flow->ram_repair) & sts) != sts);
- timer_monotonic_get(&t2);
+ stopwatch_init(&sw);
+ while ((read32(&flow->ram_repair) & sts) != sts)
+ ;
printk(BIOS_DEBUG, "RAM repair complete in %ld usecs.\n",
- mono_time_diff_microseconds(&t1, &t2));
+ stopwatch_duration_usecs(&sw));
}
void ccplex_cpu_prepare(void)
diff --git a/src/soc/nvidia/tegra132/spi.c b/src/soc/nvidia/tegra132/spi.c
index 973bdc94ea..882a6ad344 100644
--- a/src/soc/nvidia/tegra132/spi.c
+++ b/src/soc/nvidia/tegra132/spi.c
@@ -416,8 +416,7 @@ static inline u32 rx_fifo_count(struct tegra_spi_channel *spi)
static int tegra_spi_pio_finish(struct tegra_spi_channel *spi)
{
u8 *p = spi->in_buf;
- struct mono_time start;
- struct rela_time rt;
+ struct stopwatch sw;
clrbits_le32(&spi->regs->command1, SPI_CMD1_RX_EN | SPI_CMD1_TX_EN);
@@ -425,12 +424,11 @@ static int tegra_spi_pio_finish(struct tegra_spi_channel *spi)
* Allow some time in case the Rx FIFO does not yet have
* all packets pushed into it. See chrome-os-partner:24215.
*/
- timer_monotonic_get(&start);
+ stopwatch_init_usecs_expire(&sw, SPI_FIFO_XFER_TIMEOUT_US);
do {
if (rx_fifo_count(spi) == spi_byte_count(spi))
break;
- rt = current_time_from(&start);
- } while (rela_time_in_microseconds(&rt) < SPI_FIFO_XFER_TIMEOUT_US);
+ } while (!stopwatch_expired(&sw));
while (!(read32(&spi->regs->fifo_status) &
SPI_FIFO_STATUS_RX_FIFO_EMPTY)) {
diff --git a/src/soc/nvidia/tegra132/timer.c b/src/soc/nvidia/tegra132/timer.c
index 4a43208f61..ed10340040 100644
--- a/src/soc/nvidia/tegra132/timer.c
+++ b/src/soc/nvidia/tegra132/timer.c
@@ -28,18 +28,18 @@ void init_timer(void)
void udelay(unsigned usec)
{
- struct mono_time current, end;
-
- if (!thread_yield_microseconds(usec))
- return;
+ struct stopwatch sw;
/*
* As the hardware clock granularity is in microseconds pad the
* requested delay by one to get at least >= requested usec delay.
*/
- timer_monotonic_get(&end);
- mono_time_add_usecs(&end, usec + 1);
- do {
- timer_monotonic_get(&current);
- } while (mono_time_before(&current, &end));
+ usec += 1;
+
+ if (!thread_yield_microseconds(usec))
+ return;
+
+ stopwatch_init_usecs_expire(&sw, usec);
+ while (!stopwatch_expired(&sw))
+ ;
}