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authorMarc Jones <marcjones@sysproconsulting.com>2021-03-05 10:53:55 -0700
committerMarc Jones <marc@marcjonesconsulting.com>2021-03-09 16:50:10 +0000
commitbab0544200403c944045237329187fda9406da2a (patch)
tree756eedcc833e176b7de1a4d5e9753ffe3950a6de /src/soc
parent3322d33e08ac19ea8ec37502c5f34acd3c4b51ec (diff)
downloadcoreboot-bab0544200403c944045237329187fda9406da2a.tar.xz
soc/intel/common/pch: Add server PCH option
Add a server Kconfig option to select a subset of common PCH devices. Client devices are included if server isn't selected. This maintains the current Kconfig behavior. Change-Id: If11d1a51192dd87ad770b8aa53ce02b6a28b8da8 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51307 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/common/pch/Kconfig31
1 files changed, 22 insertions, 9 deletions
diff --git a/src/soc/intel/common/pch/Kconfig b/src/soc/intel/common/pch/Kconfig
index 644fed1f4d..1ad72d8e44 100644
--- a/src/soc/intel/common/pch/Kconfig
+++ b/src/soc/intel/common/pch/Kconfig
@@ -10,27 +10,30 @@ config SOC_INTEL_COMMON_PCH_BASE
code now having option to select required base PCH block to include
common IP block.
+config SOC_INTEL_COMMON_PCH_SERVER
+ def_bool n
+ depends on SOC_INTEL_COMMON_PCH_BASE
+ help
+ SERVER is a subset of the COMMON_PCH_BASE and limits support to
+ server PCH devices (ex:, Intel C620 - Lewisburg).
+
if SOC_INTEL_COMMON_PCH_BASE
source "src/soc/intel/common/pch/*/Kconfig"
-config PCH_SPECIFIC_OPTIONS
+config PCH_SPECIFIC_BASE_OPTIONS
+ # Always include the BASE (SERVER) subset of devices
def_bool y
select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
select SOC_INTEL_COMMON_BLOCK_CSE
- select SOC_INTEL_COMMON_BLOCK_DSP
select SOC_INTEL_COMMON_BLOCK_DMI
select SOC_INTEL_COMMON_BLOCK_FAST_SPI
select SOC_INTEL_COMMON_BLOCK_GPIO
select SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG
- select SOC_INTEL_COMMON_BLOCK_GRAPHICS
select SOC_INTEL_COMMON_BLOCK_ITSS
- select SOC_INTEL_COMMON_BLOCK_I2C
select SOC_INTEL_COMMON_BLOCK_LPC
select SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_DMI
- select SOC_INTEL_COMMON_BLOCK_LPSS
select SOC_INTEL_COMMON_BLOCK_P2SB
- select SOC_INTEL_COMMON_BLOCK_PCIE
select SOC_INTEL_COMMON_BLOCK_PCR
select SOC_INTEL_COMMON_BLOCK_PMC
select SOC_INTEL_COMMON_BLOCK_RTC
@@ -40,10 +43,20 @@ config PCH_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK_TCO
select SOC_INTEL_COMMON_BLOCK_TCO_ENABLE_THROUGH_SMBUS
select SOC_INTEL_COMMON_BLOCK_TIMER
- select SOC_INTEL_COMMON_BLOCK_UART
- select SOC_INTEL_COMMON_BLOCK_XDCI
select SOC_INTEL_COMMON_BLOCK_XHCI
select SOC_INTEL_COMMON_PCH_LOCKDOWN
select SOUTHBRIDGE_INTEL_COMMON_SMBUS
-endif
+config PCH_SPECIFIC_CLIENT_OPTIONS
+ # Include the CLIENT devices if this is not a SERVER
+ def_bool n if SOC_INTEL_COMMON_PCH_SERVER
+ def_bool y if !SOC_INTEL_COMMON_PCH_SERVER
+ select SOC_INTEL_COMMON_BLOCK_DSP
+ select SOC_INTEL_COMMON_BLOCK_GRAPHICS
+ select SOC_INTEL_COMMON_BLOCK_I2C
+ select SOC_INTEL_COMMON_BLOCK_LPSS
+ select SOC_INTEL_COMMON_BLOCK_PCIE
+ select SOC_INTEL_COMMON_BLOCK_UART
+ select SOC_INTEL_COMMON_BLOCK_XDCI
+
+endif # SOC_INTEL_COMMON_PCH_BASE