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authorJohn Zhao <john.zhao@intel.com>2020-09-21 13:10:11 -0700
committerTim Wawrzynczak <twawrzynczak@chromium.org>2020-09-24 18:48:44 +0000
commitc16fc8a49c4bae8da2b496dd8a59056ac57483f9 (patch)
treecf5ec061a3f57ea05d88bc3d61a1d8f3d58e7abe /src/soc
parent7626e4b3aee940648387840bb7942b3d7ca79314 (diff)
downloadcoreboot-c16fc8a49c4bae8da2b496dd8a59056ac57483f9.tar.xz
soc/intel/tigerlake: Add support for CnviBtCore and CnviBtAudioOffload
This change adds configuration support for both of CnviBtCore and CnviBtAudioOffload. BUG=b:169045123 TEST=Built and boot up to kernel on Volteer. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: Id4bf41f07c4a53de17e9eb91a8ddfb1083cbf83e Reviewed-on: https://review.coreboot.org/c/coreboot/+/45585 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-by: Naveen M <naveen.m@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/tigerlake/fsp_params.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c
index 1c5490b0f8..38f444bbd5 100644
--- a/src/soc/intel/tigerlake/fsp_params.c
+++ b/src/soc/intel/tigerlake/fsp_params.c
@@ -270,6 +270,13 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
dev = pcidev_path_on_root(PCH_DEVFN_CNVI_WIFI);
params->CnviMode = is_dev_enabled(dev);
+ /* CNVi BT Core */
+ dev = pcidev_path_on_root(PCH_DEVFN_CNVI_BT);
+ params->CnviBtCore = is_dev_enabled(dev);
+
+ /* CNVi BT Audio Offload */
+ params->CnviBtAudioOffload = config->CnviBtAudioOffload;
+
/* VMD */
dev = pcidev_path_on_root(SA_DEVFN_VMD);
params->VmdEnable = is_dev_enabled(dev);