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authorKenji Chen <kenji.chen@intel.com>2014-09-26 02:48:16 +0800
committerPatrick Georgi <pgeorgi@google.com>2015-04-02 17:27:47 +0200
commitc373f503dbbfc2a70e91f576fac01f66126556c2 (patch)
tree2866ebb7d4d611d2fcbe149153bc849f6c66d508 /src/soc
parent8ef55ee9969de3003eae9e3113b7497799ba14ec (diff)
downloadcoreboot-c373f503dbbfc2a70e91f576fac01f66126556c2.tar.xz
Broadwell: Synchronize RO, Link Arbiter, and OBFF with FRC
OBFF: Disable it by clearing bit fields in that W/O register. RO: Enable Relaxed Ordering from each enabled Root Port. Linker Arbiter: Set it to recommended setting. BUG=None TEST=Build an image and check the setting are applied correctly on Samus. Signed-off-by: Kenji Chen <kenji.chen@intel.com> Change-Id: I7a72217729d6f6ff5320738245c380c887c5912f Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 465b0a37c381930a4f0d74cd4fd69503a082911b Original-Change-Id: I284e9eba1c2fceb690d3ef48b45a6f36d07ff84c Original-Reviewed-on: https://chromium-review.googlesource.com/219993 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Commit-Queue: Kenji Chen <kenji.chen@intel.com> Original-Tested-by: Kenji Chen <kenji.chen@intel.com> Reviewed-on: http://review.coreboot.org/9210 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/broadwell/pcie.c9
1 files changed, 7 insertions, 2 deletions
diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c
index 22eaab9c5d..b14ad9dea0 100644
--- a/src/soc/intel/broadwell/pcie.c
+++ b/src/soc/intel/broadwell/pcie.c
@@ -523,8 +523,8 @@ static void pch_pcie_early(struct device *dev)
pcie_update_cfg(dev, 0x338, ~(1 << 26), 0);
}
- /* Enable LTR in Root Port. */
- pcie_update_cfg(dev, 0x64, ~(1 << 11), (1 << 11));
+ /* Enable LTR in Root Port. Disable OBFF. */
+ pcie_update_cfg(dev, 0x64, ~(1 << 11) & ~(3 << 18), (1 << 11));
pcie_update_cfg(dev, 0x68, ~(1 << 10), (1 << 10));
pcie_update_cfg(dev, 0x318, ~(0xffff << 16), (0x1414 << 16));
@@ -550,6 +550,11 @@ static void pch_pcie_early(struct device *dev)
/* Set Extended Capability to offset 200h and Advanced Error Report. */
pcie_update_cfg(dev, 0x100, ~(1 << 29) & ~0xfffff, (1 << 29) | 0x10001);
+ pcie_update_cfg(dev, 0x320, ~(3 << 20) & ~(7 << 6),
+ (1 << 20) | (3 << 6));
+ /* Enable Relaxed Order from Root Port. */
+ pcie_update_cfg(dev, 0x320, ~(3 << 23), (3 << 23));
+
if (rp == 1 || rp == 5 || rp == 6)
pcie_update_cfg8(dev, 0xf7, ~0xc, 0);