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authorArthur Heymans <arthur@aheymans.xyz>2020-10-19 16:36:30 +0200
committerAngel Pons <th3fanbus@gmail.com>2020-11-20 00:44:30 +0000
commitc660600e420a3fe2fb41387d332403933d6dfe8a (patch)
tree86648689e311d2ff8b6019a73bba638b44ca5bb3 /src/soc
parentc28f0e08024296b72f95f3475ff14ef22ccec046 (diff)
downloadcoreboot-c660600e420a3fe2fb41387d332403933d6dfe8a.tar.xz
soc/intel/xeon_sp/{skx,cpx}: Add txt_get_chipset_dpr callback
Change-Id: Id824324325d05b52fb2b9ced04fd3539cc37bd55 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46555 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h1
-rw-r--r--src/soc/intel/xeon_sp/memmap.c47
-rw-r--r--src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h1
3 files changed, 49 insertions, 0 deletions
diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h
index 33e257cb7c..98c47fc5f0 100644
--- a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h
+++ b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h
@@ -69,6 +69,7 @@
#define VTD_CAP_LOW 0x08
#define VTD_CAP_HIGH 0x0C
#define VTD_EXT_CAP_HIGH 0x14
+#define VTD_LTDPR 0x290
/* CPU Devices */
#define CBDMA_DEV_NUM 0x04
diff --git a/src/soc/intel/xeon_sp/memmap.c b/src/soc/intel/xeon_sp/memmap.c
index edc62cf881..cd817540b7 100644
--- a/src/soc/intel/xeon_sp/memmap.c
+++ b/src/soc/intel/xeon_sp/memmap.c
@@ -5,7 +5,10 @@
#include <console/console.h>
#include <device/pci_ops.h>
#include <cpu/x86/smm.h>
+#include <soc/soc_util.h>
#include <soc/pci_devs.h>
+#include <soc/util.h>
+#include <security/intel/txt/txt_platform.h>
void smm_region(uintptr_t *start, size_t *size)
{
@@ -41,3 +44,47 @@ void fill_postcar_frame(struct postcar_frame *pcf)
if (CONFIG(TSEG_STAGE_CACHE))
postcar_enable_tseg_cache(pcf);
}
+
+#if !defined(__SIMPLE_DEVICE__)
+union dpr_register txt_get_chipset_dpr(void)
+{
+ const IIO_UDS *hob = get_iio_uds();
+ union dpr_register dpr;
+ struct device *dev = VTD_DEV(0);
+
+ dpr.raw = 0;
+
+ if (dev == NULL) {
+ printk(BIOS_ERR, "BUS 0: Unable to find VTD PCI dev");
+ return dpr;
+ }
+
+ dpr.raw = pci_read_config32(dev, VTD_LTDPR);
+
+ /* Compare the LTDPR register on all iio stacks */
+ for (int socket = 0; socket < hob->PlatformData.numofIIO; ++socket) {
+ for (int stack = 0; stack < MAX_IIO_STACK; ++stack) {
+ const STACK_RES *ri =
+ &hob->PlatformData.IIO_resource[socket].StackRes[stack];
+ if (!is_iio_stack_res(ri))
+ continue;
+ uint8_t bus = ri->BusBase;
+ dev = VTD_DEV(bus);
+
+ if (dev == NULL) {
+ printk(BIOS_ERR, "BUS %x: Unable to find VTD PCI dev\n", bus);
+ dpr.raw = 0;
+ return dpr;
+ }
+
+ union dpr_register test_dpr = { .raw = pci_read_config32(dev, VTD_LTDPR) };
+ if (dpr.raw != test_dpr.raw) {
+ printk(BIOS_ERR, "LTDPR not the same on all IIO's");
+ dpr.raw = 0;
+ return dpr;
+ }
+ }
+ }
+ return dpr;
+}
+#endif
diff --git a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h
index 429278c36b..cd5d553755 100644
--- a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h
+++ b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h
@@ -93,6 +93,7 @@
#define VTD_CAP_LOW 0x08
#define VTD_CAP_HIGH 0x0C
#define VTD_EXT_CAP_HIGH 0x14
+#define VTD_LTDPR 0x290
#define PCU_CR1_C2C3TT_REG 0xdc
#define PCU_CR1_PCIE_ILTR_OVRD 0xfc