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authorKarthikeyan Ramasubramanian <kramasub@google.com>2020-09-18 01:34:27 -0600
committerKarthik Ramasubramanian <kramasub@google.com>2020-09-21 15:49:16 +0000
commitcc05e311a26132abe3139d4c5f2bc36db5a738d1 (patch)
tree9409890cfb9c2dda8dafae382bd3e4e5e3fbcc02 /src/soc
parentbe710767fd34e72af399ec2985f788e4054939f8 (diff)
downloadcoreboot-cc05e311a26132abe3139d4c5f2bc36db5a738d1.tar.xz
soc/intel/common/cse_lite: Defer cse_fw_sync for JSL
Defer cse_fw_sync to BS_DEV_RESOURCES boot state so that MRC training data can be cached before CSE FW Sync and a second MRC training can be avoided. BUG=b:168850641 TEST=Build and boot the waddledoo board to OS. Ensure that the memory training is performed only once. Change-Id: I0ef5693eaa6ed34dc08c94e5db153f4295578f5f Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45515 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/common/block/cse/cse_lite.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c
index 7daa35eb9b..c9e4e1f470 100644
--- a/src/soc/intel/common/block/cse/cse_lite.c
+++ b/src/soc/intel/common/block/cse/cse_lite.c
@@ -751,7 +751,7 @@ void cse_fw_sync(void *unused)
}
}
-#if CONFIG(SOC_INTEL_TIGERLAKE)
+#if CONFIG(SOC_INTEL_TIGERLAKE) || CONFIG(SOC_INTEL_JASPERLAKE)
/*
* This needs to happen after the MRC cache write to avoid a 2nd
* memory training sequence.