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authorKyösti Mälkki <kyosti.malkki@gmail.com>2017-07-30 11:37:14 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2017-08-07 12:35:33 +0000
commitd1a0c5770803e45dabecf6094fccb9895ea76d10 (patch)
tree8c949297438a11ebdc39d0ea148ef24559917df8 /src/soc
parentab1d2ac626d0535191b5f612707ae8f22c46c538 (diff)
downloadcoreboot-d1a0c5770803e45dabecf6094fccb9895ea76d10.tar.xz
usbdebug: Consolidate EHCI_BAR setup
There is assumption of static EHCI_BAR_INDEX, try to clean it up by bringing BAR programming at one spot. Change-Id: Ie16090536ac5470c24720a54813015250ae2d0dd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20825 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/amd/stoneyridge/enable_usbdebug.c4
-rw-r--r--src/soc/intel/broadwell/usb_debug.c8
2 files changed, 0 insertions, 12 deletions
diff --git a/src/soc/amd/stoneyridge/enable_usbdebug.c b/src/soc/amd/stoneyridge/enable_usbdebug.c
index 675f4b7870..db1e4cf231 100644
--- a/src/soc/amd/stoneyridge/enable_usbdebug.c
+++ b/src/soc/amd/stoneyridge/enable_usbdebug.c
@@ -53,8 +53,4 @@ void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base)
/* Enable all of the USB controllers */
outb(0xEF, PM_INDEX);
outb(0x7F, PM_DATA);
-
- pci_write_config32(dev, EHCI_BAR_INDEX, base);
- pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY
- | PCI_COMMAND_MASTER);
}
diff --git a/src/soc/intel/broadwell/usb_debug.c b/src/soc/intel/broadwell/usb_debug.c
index 683b4cc522..b19462dc3e 100644
--- a/src/soc/intel/broadwell/usb_debug.c
+++ b/src/soc/intel/broadwell/usb_debug.c
@@ -41,12 +41,4 @@ void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base)
{
- if (!dev)
- return;
-
- /* Set the EHCI BAR address. */
- pci_write_config32(dev, EHCI_BAR_INDEX, base);
-
- /* Enable access to the EHCI memory space registers. */
- pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
}