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authorLijian Zhao <lijian.zhao@intel.com>2017-07-14 11:09:10 -0700
committerMartin Roth <martinroth@google.com>2017-07-21 15:56:16 +0000
commitdbe7f893c0e3fffc4e9862d872d65df752feaf9d (patch)
tree2d0d3e2fd4f7d5313026440a62208cb40428bcd0 /src/soc
parent399c022a8c6cba7ad6d75fdf377a690395877611 (diff)
downloadcoreboot-dbe7f893c0e3fffc4e9862d872d65df752feaf9d.tar.xz
soc/intel/cannonlake: Call into FSP siliconinit
The following changes can make system call into FSP siliconinit and exit from that until payloads. 1. Add frame to call fspsinit. 2. Temporarily set all the USB OC pin to 0 to pass FSP siliconinit. Change-Id: I1c9c35ececf3c28d7a024f10a5d326700cc8ac49 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/20581 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/cannonlake/Makefile.inc3
-rw-r--r--src/soc/intel/cannonlake/chip.c59
-rw-r--r--src/soc/intel/cannonlake/chip.h28
-rw-r--r--src/soc/intel/cannonlake/include/soc/ramstage.h28
4 files changed, 117 insertions, 1 deletions
diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc
index e427f98929..f166f1a3fc 100644
--- a/src/soc/intel/cannonlake/Makefile.inc
+++ b/src/soc/intel/cannonlake/Makefile.inc
@@ -16,7 +16,8 @@ romstage-y += cbmem.c
romstage-y += reset.c
romstage-$(CONFIG_UART_DEBUG) += uart.c
-ramstage-y += cbmem.c
+ramstage-y += chip.c
+ramstage-y += memmap.c
ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c
ramstage-$(CONFIG_UART_DEBUG) += uart.c
diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c
new file mode 100644
index 0000000000..2f893e3d48
--- /dev/null
+++ b/src/soc/intel/cannonlake/chip.c
@@ -0,0 +1,59 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016-2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <chip.h>
+#include <console/console.h>
+#include <device/pci.h>
+#include <fsp/api.h>
+#include <fsp/api.h>
+#include <fsp/util.h>
+#include <romstage_handoff.h>
+#include <soc/ramstage.h>
+#include <string.h>
+
+void soc_init_pre_device(void *chip_info)
+{
+ /* Perform silicon specific init. */
+ fsp_silicon_init(romstage_handoff_is_resume());
+}
+
+struct chip_operations soc_intel_cannonlake_ops = {
+ CHIP_NAME("Intel Cannonlake")
+ .init = &soc_init_pre_device,
+};
+
+/* UPD parameters to be initialized before SiliconInit */
+void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
+{
+ int i;
+ FSP_S_CONFIG *params = &supd->FspsConfig;
+
+ /* Set USB OC pin to 0 first */
+ for (i = 0; i < ARRAY_SIZE(params->Usb2OverCurrentPin); i++) {
+ params->Usb2OverCurrentPin[i] = 0;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(params->Usb3OverCurrentPin); i++) {
+ params->Usb3OverCurrentPin[i] = 0;
+ }
+
+ mainboard_silicon_init_params(params);
+}
+
+/* Mainboard GPIO Configuration */
+__attribute__((weak)) void mainboard_silicon_init_params(FSP_S_CONFIG *params)
+{
+ printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
+}
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
new file mode 100644
index 0000000000..bbc58808a3
--- /dev/null
+++ b/src/soc/intel/cannonlake/chip.h
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_CHIP_H_
+#define _SOC_CHIP_H_
+
+#include <stdint.h>
+
+struct soc_intel_cannonlake_config {
+};
+
+typedef struct soc_intel_cannonlake_config config_t;
+
+#endif
diff --git a/src/soc/intel/cannonlake/include/soc/ramstage.h b/src/soc/intel/cannonlake/include/soc/ramstage.h
new file mode 100644
index 0000000000..4a96185e6b
--- /dev/null
+++ b/src/soc/intel/cannonlake/include/soc/ramstage.h
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015-2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_RAMSTAGE_H_
+#define _SOC_RAMSTAGE_H_
+
+#include <chip.h>
+#include <device/device.h>
+#include <fsp/api.h>
+#include <fsp/util.h>
+
+void mainboard_silicon_init_params(FSP_S_CONFIG *params);
+void soc_init_pre_device(void *chip_info);
+
+#endif