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authorNico Huber <nico.h@gmx.de>2019-05-04 17:17:40 +0200
committerPatrick Georgi <pgeorgi@google.com>2019-05-07 15:57:51 +0000
commitec562161cd2265c924482835fd2ab32c13ba587e (patch)
treec62582361b3b4537da22d96fbf608eaae1f21c38 /src/soc
parentf98f8ebb8cb43f17c8d244f2c4cce2e257355e37 (diff)
downloadcoreboot-ec562161cd2265c924482835fd2ab32c13ba587e.tar.xz
soc/intel/bsw: Move memory init values into `romstage.h`
`chip.h` is usually used as devicetree interface. Change-Id: Ied30927d68927b86758a84ccf3f5fbd8cce632f1 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32592 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/braswell/chip.h3
-rw-r--r--src/soc/intel/braswell/include/soc/romstage.h4
2 files changed, 4 insertions, 3 deletions
diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h
index bb06dd595a..5a00328f4d 100644
--- a/src/soc/intel/braswell/chip.h
+++ b/src/soc/intel/braswell/chip.h
@@ -32,9 +32,6 @@
#define SVID_CONFIG3 3
#define SVID_PMIC_CONFIG 8
-#define MEM_DDR3 0
-#define MEM_LPDDR3 1
-
enum lpe_clk_src {
LPE_CLK_SRC_XTAL,
LPE_CLK_SRC_PLL,
diff --git a/src/soc/intel/braswell/include/soc/romstage.h b/src/soc/intel/braswell/include/soc/romstage.h
index 8fa9c8a713..2512430f75 100644
--- a/src/soc/intel/braswell/include/soc/romstage.h
+++ b/src/soc/intel/braswell/include/soc/romstage.h
@@ -34,4 +34,8 @@ void set_max_freq(void);
void program_base_addresses(void);
int chipset_prev_sleep_state(struct chipset_power_state *ps);
+/* Values for FSP's PcdMemoryTypeEnable */
+#define MEM_DDR3 0
+#define MEM_LPDDR3 1
+
#endif /* _SOC_ROMSTAGE_H_ */