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authorFrans Hendriks <fhendriks@eltan.com>2018-10-31 10:07:11 +0100
committerPatrick Georgi <pgeorgi@google.com>2018-11-28 11:46:43 +0000
commitf01a15952adb903fed169dbcef1e4a33cc88ba3f (patch)
treeb7eea269144cf2be3b4a15c5974f9aa5604a9146 /src/soc
parentad19c2f58bcf30af87795543d5667d47e421558e (diff)
downloadcoreboot-f01a15952adb903fed169dbcef1e4a33cc88ba3f.tar.xz
src/soc/intel/braswell/acpi/lpc.asl: Add ACPI and GPIO bases
ACPI and GPIO base are used by LPC controller, but not reserved. Both bases are added to the LPC device resources. BUG=N/A TEST=Intel CherryHill CRB Change-Id: I5248694b497c4965d79dd7c25ec97592dc0dddbc Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/29288 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/braswell/acpi/lpc.asl4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/braswell/acpi/lpc.asl b/src/soc/intel/braswell/acpi/lpc.asl
index ce83009a1b..067b05f6de 100644
--- a/src/soc/intel/braswell/acpi/lpc.asl
+++ b/src/soc/intel/braswell/acpi/lpc.asl
@@ -106,6 +106,10 @@ Device (LPCB)
IO (Decode16, 0x80, 0x80, 0x1, 0x01) /* Port 80 Post */
IO (Decode16, 0x92, 0x92, 0x1, 0x01) /* CPU Reserved */
IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) /* SWSMI */
+ IO (Decode16, ACPI_BASE_ADDRESS, ACPI_BASE_ADDRESS,
+ 0x1, ACPI_BASE_SIZE) /* ACPI Base */
+ IO (Decode16, GPIO_BASE_ADDRESS, GPIO_BASE_ADDRESS,
+ 0x1, 0xff) /* GPIO Base */
})
Method (_CRS, 0, NotSerialized)