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authorLijian Zhao <lijian.zhao@intel.com>2018-02-09 13:01:39 -0800
committerMartin Roth <martinroth@google.com>2018-02-14 17:01:25 +0000
commitf1b1d92854281b035851719741092388f70e00f0 (patch)
tree924a3776ee43bee23e345b5c3cf5d98b0b1985b1 /src/soc
parent2242919177317dd7827a4fc8f04c17dd8a4f8b32 (diff)
downloadcoreboot-f1b1d92854281b035851719741092388f70e00f0.tar.xz
intel/fsp: Update cannonlake fsp header
Update Cannonlake FSP header to revision 7.x.25.31. Following changes had been made: 1. Add PeciSxRest option. 2. Add Thermal Velocity Boost option. 3. Add VR power deliver design option. 4. Match MrcChannelSts. TEST=NONE Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: I32e976eacf39d2cd75f8288c86d1de1a54c194c6 Reviewed-on: https://review.coreboot.org/23677 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/cannonlake/romstage/romstage.c7
1 files changed, 0 insertions, 7 deletions
diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c
index 36cefb9b0b..759c2c9b43 100644
--- a/src/soc/intel/cannonlake/romstage/romstage.c
+++ b/src/soc/intel/cannonlake/romstage/romstage.c
@@ -40,13 +40,6 @@ static struct chipset_power_state power_state CAR_GLOBAL;
0x8d, 0x09, 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23 \
}
-/* Memory Channel Present Status */
-enum {
- CHANNEL_NOT_PRESENT,
- CHANNEL_DISABLED,
- CHANNEL_PRESENT
-};
-
/* Save the DIMM information for SMBIOS table 17 */
static void save_dimm_info(void)
{