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| author | Lijian Zhao <lijian.zhao@intel.com> | 2017-11-09 15:01:33 -0800 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-11-13 17:39:41 +0000 |
| commit | f3885618d91d47be8d6ffddeb4118d7027863c64 (patch) | |
| tree | 1744883ed2c10edaa9eb09f3fcd84aecce890ce4 /src/soc | |
| parent | 290a59284e97498f6cc879ec5638af87d4538b80 (diff) | |
| download | coreboot-f3885618d91d47be8d6ffddeb4118d7027863c64.tar.xz | |
soc/intel/cannonlake: Define default LPSS clock
Default LPSS clock need to be defined for SOC.
TEST=Turn on COMMON_I2C_DEBUG, add I2C clock entry and check I2C
programing properly during coreboot.
Change-Id: I2c6b9bb23950b09f6f05e3ef762ccb1a260efc5f
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/cannonlake/Kconfig | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 36ea922ba9..f4d524a925 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -131,6 +131,10 @@ config CPU_BCLK_MHZ int default 100 +config SOC_INTEL_COMMON_LPSS_CLOCK_MHZ + int + default 120 + config SOC_INTEL_COMMON_BLOCK_GSPI_MAX int default 3 |