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authorSubrata Banik <subrata.banik@intel.com>2020-01-22 15:58:39 +0530
committerSubrata Banik <subrata.banik@intel.com>2020-01-26 03:00:41 +0000
commitfa8f9ecc69a9077b6237c33fb38365806439947b (patch)
treeb9893923f624d420c4cffdaf62cc51387340c8eb /src/soc
parentf895dade61c9273712dcd122e6be5efc2d033bf0 (diff)
downloadcoreboot-fa8f9ecc69a9077b6237c33fb38365806439947b.tar.xz
soc/intel/skylake: Only reserve TPM area for !CONFIG_TPM_CR50 device
As per PC client TPM specification, the TPM description contains the base address of the TIS interface 0xfed40000 and the size of the MMIO area is 20KB (0x5000). Hence ACPI used to reserve those fixed system memory from getting used by OS. Platform with TPM_CR50 doesn't require fixed SoC mapped memory hence additional reservation might not required. TEST=Build and boot EVE and Soraka to OS. Change-Id: Id02a2659ce42f705180370000df89d4f6b64afce Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38512 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/skylake/acpi/systemagent.asl2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/acpi/systemagent.asl b/src/soc/intel/skylake/acpi/systemagent.asl
index 3902b93749..c4d8a706bc 100644
--- a/src/soc/intel/skylake/acpi/systemagent.asl
+++ b/src/soc/intel/skylake/acpi/systemagent.asl
@@ -182,11 +182,13 @@ Method (_CRS, 0, Serialized)
0x00000000, PCH_PRESERVED_BASE_ADDRESS, 0xfe7fffff,
0x00000000, PCH_PRESERVED_BASE_SIZE)
+#if !CONFIG(TPM_CR50)
/* TPM Area (0xfed40000-0xfed44fff) */
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0xfed40000, 0xfed44fff, 0x00000000,
0x00005000)
+#endif
})
/* Find PCI resource area in MCRS */