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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-09-25 15:22:42 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-09-30 08:31:33 +0000
commit01b60633a85495bf9041f61176fa26198a4eca54 (patch)
tree33c4148e67b847d9262ce19a8fa6f595162f3258 /src/soc
parent3356305ca6cd72b6b92dd4e8ebbba2b828574b8e (diff)
downloadcoreboot-01b60633a85495bf9041f61176fa26198a4eca54.tar.xz
soc/intel/fsp_baytrail: Drop some __BOOTBLOCK__ guards
Change in ssus_disable_internal_pull() is for romcc compatibility. Change-Id: Ib72a669a3b5cd90e74d917f74f35453a85941658 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35600 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/fsp_baytrail/include/soc/gpio.h15
1 files changed, 6 insertions, 9 deletions
diff --git a/src/soc/intel/fsp_baytrail/include/soc/gpio.h b/src/soc/intel/fsp_baytrail/include/soc/gpio.h
index 68c62350ce..137ec95f14 100644
--- a/src/soc/intel/fsp_baytrail/include/soc/gpio.h
+++ b/src/soc/intel/fsp_baytrail/include/soc/gpio.h
@@ -313,8 +313,6 @@
#define GPSSUS_GPIO_F1_RANGE_START 11
#define GPSSUS_GPIO_F1_RANGE_END 21
-#ifndef __BOOTBLOCK__
-
struct soc_gpio_map {
u32 pad_conf0;
u32 pad_conf1;
@@ -360,8 +358,6 @@ void write_ssus_gpio(uint8_t gpio_num, uint8_t val);
void configure_ssus_gpio(uint8_t gpio_num, uint32_t pconf0, uint32_t pad_val);
void configure_score_gpio(uint8_t gpio_num, uint32_t pconf0, uint32_t pad_val);
-#endif /* #ifndef __BOOTBLOCK__ */
-
/* Functions / defines for changing GPIOs in romstage */
/* SCORE Pad definitions. */
#define UART_RXD_PAD 82
@@ -401,7 +397,6 @@ static inline void ssus_select_func(int pad, int func)
write32(pconf0_addr, reg);
}
-#ifndef __BOOTBLOCK__
/* These functions require that the input pad be configured as an input GPIO */
static inline int score_get_gpio(int pad)
@@ -436,10 +431,12 @@ static inline void ssus_set_gpio(int pad, int val)
static inline void ssus_disable_internal_pull(int pad)
{
- const uint32_t pull_mask = ~(0xf << 7);
- write32(ssus_pconf0(pad), read32(ssus_pconf0(pad)) & pull_mask);
-}
+ uint32_t reg;
+ uint32_t *pconf0_addr = ssus_pconf0(pad);
-#endif /* #ifndef __BOOTBLOCK__ */
+ reg = read32(pconf0_addr);
+ reg &= ~(0xf << 7);
+ write32(pconf0_addr, reg);
+}
#endif /* _BAYTRAIL_GPIO_H_ */