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authorFurquan Shaikh <furquan@google.com>2018-03-01 15:21:05 -0800
committerFurquan Shaikh <furquan@google.com>2018-03-05 17:55:32 +0000
commit10c3b96ac74cf00b44fca40c83c7b13964cff08c (patch)
tree9c8b24830a0596cdd588120d2fb2c5b9278a3efc /src/soc
parent591be2d58128c4469f6c3c48725874fab60b1c5b (diff)
downloadcoreboot-10c3b96ac74cf00b44fca40c83c7b13964cff08c.tar.xz
soc/intel/common/block/smm: Add configurable delay before entering S5
This change adds a configurable delay in milliseconds before SLP_EN is set in SLP_SMI for S5. Reason for doing this is to avoid race between SLP and power button SMIs. On some platforms (Nami, Nautilus), it was observed that power button SMI triggered by EC was competing with the SLP SMI triggered by keyboard driver. Keyboard driver indicated power button press which resulted in depthcharge triggering SLP_SMI, causing the AP to enter S5. However, the power button press also causes the EC to send a pulse on PWRBTN# line, which is debounced for 16ms before an interrupt is triggered. This interrupt was generated after SLP_SMI is processed which resulted in the device waking back up from S5. This change adds a config option SOC_INTEL_COMMON_BLOCK_SMM_S5_DELAY_MS which is used to add a delay before SLP_EN is set for S5. This change should only affect CHROMEOS boards as the config option will be 0 in other cases. BUG=b:74083107 TEST=Verified that nami, nautilus do not wake back from S5 on power button press at dev mode screen. Change-Id: Iaee19b5aba0aad7eb34bd126fda5b0f6ef394ed7 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/24964 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/common/block/smm/Kconfig9
-rw-r--r--src/soc/intel/common/block/smm/smihandler.c18
2 files changed, 27 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/smm/Kconfig b/src/soc/intel/common/block/smm/Kconfig
index 035578003a..909382e0ee 100644
--- a/src/soc/intel/common/block/smm/Kconfig
+++ b/src/soc/intel/common/block/smm/Kconfig
@@ -7,3 +7,12 @@ config SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
bool
help
Intel Processor trap flag if it is supported
+
+config SOC_INTEL_COMMON_BLOCK_SMM_S5_DELAY_MS
+ int
+ default 100 if CHROMEOS
+ default 0
+ help
+ Time in milliseconds that SLP_SMI for S5 waits for before
+ enabling sleep. This is required to avoid any race between
+ SLP_SMI and PWRBTN SMI.
diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c
index 81ff3ebec8..d492459dc8 100644
--- a/src/soc/intel/common/block/smm/smihandler.c
+++ b/src/soc/intel/common/block/smm/smihandler.c
@@ -19,6 +19,7 @@
#include <console/console.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/smm.h>
+#include <delay.h>
#include <device/pci_def.h>
#include <elog.h>
#include <intelblocks/fast_spi.h>
@@ -219,6 +220,23 @@ void smihandler_southbridge_sleep(
pmc_soc_restore_power_failure();
/* also iterates over all bridges on bus 0 */
busmaster_disable_on_bus(0);
+
+ /*
+ * Some platforms (e.g. Chromebooks) have observed race between
+ * SLP SMI and PWRBTN SMI because of the way these SMIs are
+ * triggered on power button press. Allow adding a delay before
+ * triggering sleep enable for S5, so that power button
+ * interrupt does not result into immediate wake.
+ */
+ mdelay(CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_S5_DELAY_MS);
+
+ /*
+ * Ensure any pending power button status bits are cleared as
+ * the system is entering S5 and doesn't want to be woken up
+ * right away from older power button events.
+ */
+ pmc_clear_pm1_status();
+
break;
default:
printk(BIOS_DEBUG, "SMI#: ERROR: SLP_TYP reserved\n");