ipq8064/storm: UART enable and various fixes

The original patch from chromium was  a bit of a mishmash.
Between that, rebasing and using the coreboot.org UART infrastructure,
the patch has changed a bit from the original. It seems reasonable to
keep these changes together.
- build in the ipq UART and turn on bootblock console
- sets LPAE and ROM header address
- adds cpd.c to storm

The original commit:
ipq8064: make UART driver work in bootblock

This patch it the last one in the chain adapting the ipq9064 UART
driver for use in coreboot. A new config option
(CONSOLE_SERIAL_IPQ806X) is being introduced to control inclusion of
the driver.

The previously introduced uart_wrapper.c is now included in the build
to provide the console driver structure used by ramstage.

Necessary configuration options are added to allow use of UART in the
bootblock.

BUG=chrome-os-partner:27784

TEST=with this change the coreboot image on AP148 prints a banner on
   start up:

coreboot-4.0 Wed Apr 23 16:24:51 PDT 2014 starting...

Original-Change-Id: I129ee30ba17a5061b30cfee56c135df31eba98b5
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/196663
(cherry picked from commit 42ca8994361327c24e7a611505b21534dd231f30)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I1175e74ed639cdc27a1a677fba65de2dd2b13a91
Reviewed-on: http://review.coreboot.org/7875
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)

2 files changed, 10 insertions, 4 deletions

diff --git a/src/soc/qualcomm/ipq806x/Kconfig b/src/soc/qualcomm/ipq806x/Kconfig
index 0fb780c643..92ef3a1d10 100644
--- a/src/soc/qualcomm/ipq806x/Kconfig
+++ b/src/soc/qualcomm/ipq806x/Kconfig
@@ -1,9 +1,12 @@
 config SOC_QC_IPQ806X
+	bool
+	default n
 	select ARCH_BOOTBLOCK_ARMV4
 	select ARCH_ROMSTAGE_ARMV7
 	select ARCH_RAMSTAGE_ARMV7
-	bool
-	default n
+	select ARM_LPAE
+	select BOOTBLOCK_CONSOLE
+	select HAVE_UART_SPECIAL
 
 if SOC_QC_IPQ806X
 
@@ -13,11 +16,11 @@ config BOOTBLOCK_ROM_OFFSET
 
 config CBFS_HEADER_ROM_OFFSET
 	hex "offset of master CBFS header in ROM"
-	default 0x221000
+	default 0x224000
 
 config CBFS_ROM_OFFSET
 	hex "offset of CBFS data in ROM"
-	default 0x221080
+	default 0x224080
 
 config MBN_ENCAPSULATION
 	depends on USE_BLOBS
diff --git a/src/soc/qualcomm/ipq806x/Makefile.inc b/src/soc/qualcomm/ipq806x/Makefile.inc
index dfbbf3d445..639b9d9f45 100644
--- a/src/soc/qualcomm/ipq806x/Makefile.inc
+++ b/src/soc/qualcomm/ipq806x/Makefile.inc
@@ -22,16 +22,19 @@ bootblock-y += cbfs.c
 bootblock-y += clock.c
 bootblock-y += gpio.c
 bootblock-y += timer.c
+bootblock-$(CONFIG_DRIVERS_UART) += uart.c
 
 romstage-y += cbfs.c
 romstage-y += clock.c
 romstage-y += gpio.c
 romstage-y += timer.c
+romstage-$(CONFIG_DRIVERS_UART) += uart.c
 
 ramstage-y += cbfs.c
 ramstage-y += clock.c
 ramstage-y += gpio.c
 ramstage-y += timer.c
+ramstage-$(CONFIG_DRIVERS_UART) += uart.c
 
 ifeq ($(CONFIG_USE_BLOBS),y)