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authorRichard Spiegel <richard.spiegel@silverbackltd.com>2018-02-07 17:04:09 -0700
committerAaron Durbin <adurbin@chromium.org>2018-02-16 16:23:59 +0000
commit126614b87b43750f4f07ccdb831f652af6acc6ce (patch)
tree10c48ad93dc41986547f476e0f3a96a242fabc7a /src/soc
parenta25283d8ae905bce31d16202c4e4d4b54051ea86 (diff)
downloadcoreboot-126614b87b43750f4f07ccdb831f652af6acc6ce.tar.xz
soc/amd/common/block/pi/amd_init_late.c: Transfer memory info to cbmem
SMBIOS structure type 17 is not being generated because memory info is not being stored to cbmem. This has to happen after AGESA AmdInitLate has run, but before SMBIOS is generated. There's a need to convert format between AGESA generated info, and what is required in cbmem. Create a procedure that transfers information between AGESA and cbmem, and call it from agesawrapper_post_device() after AmdLateInit is called. BUG=b:65403853 TEST=build and run kahlee, verify if SMBIOS structure type 17 is being generated, and if associated strings are what should be expected. Change-Id: I151a8f1348c9bafceb38bab1f79d3002c5f6b31b Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/23644 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/amd/common/block/pi/amd_late_init.c64
1 files changed, 64 insertions, 0 deletions
diff --git a/src/soc/amd/common/block/pi/amd_late_init.c b/src/soc/amd/common/block/pi/amd_late_init.c
index 3695ce4f51..9d0bb269b8 100644
--- a/src/soc/amd/common/block/pi/amd_late_init.c
+++ b/src/soc/amd/common/block/pi/amd_late_init.c
@@ -19,10 +19,74 @@
#include <device/device.h>
#include <device/pci_def.h>
#include <device/pci_ops.h>
+#include <cbmem.h>
+#include <memory_info.h>
#include <amdblocks/agesawrapper.h>
#include <amdblocks/agesawrapper_call.h>
+static void transfer_memory_info(TYPE17_DMI_INFO *dmi17, struct dimm_info *dimm)
+{
+ size_t len, destlen;
+ uint32_t offset;
+
+
+ len = strnlen(dmi17->SerialNumber, sizeof(dmi17->SerialNumber)) + 1;
+ destlen = sizeof(dimm->serial);
+
+ if (len > destlen) {
+ offset = len - destlen;
+ len = destlen;
+ } else
+ offset = 0;
+
+ strncpy((char *)dimm->serial, &dmi17->SerialNumber[offset], len);
+ dimm->dimm_size = dmi17->ExtSize;
+ dimm->ddr_type = dmi17->MemoryType;
+ dimm->ddr_frequency = dmi17->Speed;
+ dimm->rank_per_dimm = dmi17->Attributes;
+ dimm->mod_type = dmi17->MemoryType;
+ dimm->bus_width = dmi17->DataWidth;
+ dimm->mod_id = dmi17->ManufacturerIdCode;
+ dimm->bank_locator = 0;
+ strncpy((char *)dimm->module_part_number, "NA",
+ sizeof(dimm->module_part_number));
+}
+
+static void prepare_dmi_17(void *unused)
+{
+ DMI_INFO *DmiTable;
+ TYPE17_DMI_INFO *address;
+ struct memory_info *mem_info;
+ struct dimm_info *dimm;
+ int i, j, dimm_cnt = 0;
+
+ mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(struct memory_info));
+ if (!mem_info) {
+ printk(BIOS_NOTICE, "Failed to add memory info to CBMEM.\n");
+ return;
+ }
+ memset(mem_info, 0, sizeof(struct memory_info));
+
+ DmiTable = agesawrapper_getlateinitptr(PICK_DMI);
+ for (i = 0; i < MAX_CHANNELS_PER_SOCKET; i++) {
+ for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
+ address = &DmiTable->T17[0][i][j];
+ if (address->Handle > 0) {
+ dimm = &mem_info->dimm[dimm_cnt];
+ dimm->channel_num = i;
+ dimm->dimm_num = j;
+ transfer_memory_info(address, dimm);
+ dimm_cnt++;
+ }
+ }
+ }
+ mem_info->dimm_cnt = dimm_cnt;
+}
+
+BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY,
+ prepare_dmi_17, NULL);
+
static void agesawrapper_post_device(void *unused)
{
if (acpi_is_wakeup_s3())