summaryrefslogtreecommitdiff
path: root/src/soc
diff options
context:
space:
mode:
authorDivya Sasidharan <divya.s.sasidharan@intel.com>2015-10-11 11:22:21 -0700
committerMartin Roth <martinroth@google.com>2016-01-14 23:09:47 +0100
commit1ff0f54f03ed0ebfd4c827bc11e31bc8309828ce (patch)
treedfc122a5319e9897122643b2583177b32240fd64 /src/soc
parentedb937acd64dbeb6b363ac5e15eb5e2e78469537 (diff)
downloadcoreboot-1ff0f54f03ed0ebfd4c827bc11e31bc8309828ce.tar.xz
soc/braswell: Add CPUID for D0 stepping
Original-Reviewed-on: https://chromium-review.googlesource.com/309122 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Tested-by: Hannah Williams <hannah.williams@intel.com> Change-Id: Ia24dbeb6b23ccbbb380843a4684def578cde168a Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Reviewed-on: https://review.coreboot.org/12727 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/braswell/cpu.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c
index 04c83847af..feb9d9b84a 100644
--- a/src/soc/intel/braswell/cpu.c
+++ b/src/soc/intel/braswell/cpu.c
@@ -149,6 +149,7 @@ static struct device_operations cpu_dev_ops = {
};
static struct cpu_device_id cpu_table[] = {
+ { X86_VENDOR_INTEL, 0x406C4 },
{ X86_VENDOR_INTEL, 0x406C3 },
{ X86_VENDOR_INTEL, 0x406C2 },
{ 0, 0 },