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authorMarc Jones <marcj303@gmail.com>2017-11-09 12:23:47 -0700
committerMarc Jones <marc@marcjonesconsulting.com>2017-11-13 17:36:37 +0000
commit31c8cdda73461f59a29457e482934cd686feed39 (patch)
tree2e80dd9343633f06ca5e42e7dd39208424029977 /src/soc
parentcc7aba7cb1d28052af53c1fe4f245792a2e4b3e7 (diff)
downloadcoreboot-31c8cdda73461f59a29457e482934cd686feed39.tar.xz
soc/amd/stoneyridge: Add GNVS variables for thermal control
BUG=b:67999819 Change-Id: I78db830c14092f5e918657e62bf38ab7124b1646 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/amd/stoneyridge/acpi/globalnvs.asl6
-rw-r--r--src/soc/amd/stoneyridge/include/soc/nvs.h8
2 files changed, 13 insertions, 1 deletions
diff --git a/src/soc/amd/stoneyridge/acpi/globalnvs.asl b/src/soc/amd/stoneyridge/acpi/globalnvs.asl
index bf0ed55249..7e696aa816 100644
--- a/src/soc/amd/stoneyridge/acpi/globalnvs.asl
+++ b/src/soc/amd/stoneyridge/acpi/globalnvs.asl
@@ -41,6 +41,12 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
PRT0, 32, // 0x25 - 0x28 - PERST_0 Address
SCDP, 8, // 0x29 - SD_CD GPIO portid
SCDO, 8, // 0x2A - GPIO pad offset relative to the community
+ TMPS, 8, // 0x2B - Temperature Sensor ID
+ TLVL, 8, // 0x2C - Throttle Level Limit
+ FLVL, 8, // 0x2D - Current FAN Level
+ TCRT, 8, // 0x2E - Critical Threshold
+ TPSV, 8, // 0x2F - Passive Threshold
+ TMAX, 8, // 0x30 - CPU Tj_max
/* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */
Offset (0x100),
#include <vendorcode/google/chromeos/acpi/gnvs.asl>
diff --git a/src/soc/amd/stoneyridge/include/soc/nvs.h b/src/soc/amd/stoneyridge/include/soc/nvs.h
index 623c554057..b4f7213eca 100644
--- a/src/soc/amd/stoneyridge/include/soc/nvs.h
+++ b/src/soc/amd/stoneyridge/include/soc/nvs.h
@@ -44,7 +44,13 @@ typedef struct global_nvs_t {
uint32_t prt0; /* 0x25 - 0x28 - PERST_0 Address */
uint8_t scdp; /* 0x29 - SD_CD GPIO portid */
uint8_t scdo; /* 0x2A - GPIO pad offset relative to the community */
- uint8_t unused[213];
+ uint8_t tmps; /* 0x2B - Temperature Sensor ID */
+ uint8_t tlvl; /* 0x2C - Throttle Level Limit */
+ uint8_t flvl; /* 0x2D - Current FAN Level */
+ uint8_t tcrt; /* 0x2E - Critical Threshold */
+ uint8_t tpsv; /* 0x2F - Passive Threshold */
+ uint8_t tmax; /* 0x30 - CPU Tj_max */
+ uint8_t unused[207];
/* ChromeOS specific (0x100 - 0xfff) */
chromeos_acpi_t chromeos;