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authorMatt DeVillier <matt.devillier@gmail.com>2018-02-18 11:39:24 -0600
committerPatrick Georgi <pgeorgi@google.com>2018-12-19 05:34:59 +0000
commit3509138476a23ddf0ec7f4ad7e37edf4438160f4 (patch)
tree4fc9229fe7d00e45f383a622a54b7d9ad849c89d /src/soc
parent3ef74493928fafa2955e3b0acecb2b625f223d83 (diff)
downloadcoreboot-3509138476a23ddf0ec7f4ad7e37edf4438160f4.tar.xz
soc/intel/skylake: Generate DMAR tables for FSP 1.1 boards
Commit c37b0e3 [soc/intel/skylake: Generate ACPI DMAR table] only generates DMAR tables for boards using FSP 2.0, which leaves out Skylake Chromebooks, which use FSP 1.1. Correct this omission by adding the same functionality for FSP 1.1 boards. Test: build/boot on U-series Skylake Chromebook, observe IOMMU fully functional with intel_iommu=on kernel parameter. Change-Id: I68837f58aac357fa3f58979fe92d8993fae58640 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/30230 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/skylake/chip.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index fb011833e4..07ac4e8fa3 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -60,7 +60,8 @@ static struct device_operations pci_domain_ops = {
.set_resources = &pci_domain_set_resources,
.scan_bus = &pci_domain_scan_bus,
#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
- .acpi_name = &soc_acpi_name,
+ .write_acpi_tables = &northbridge_write_acpi_tables,
+ .acpi_name = &soc_acpi_name,
#endif
};