summaryrefslogtreecommitdiff
path: root/src/soc
diff options
context:
space:
mode:
authorWonkyu Kim <wonkyu.kim@intel.com>2020-03-20 12:17:14 -0700
committerPatrick Georgi <pgeorgi@google.com>2020-04-14 10:05:50 +0000
commit3ba64ca3d1b055d8b4f788bc1eff4d4fedc2ec24 (patch)
tree6fdadab66e86270b0cc14c18621dc76aa217d21d /src/soc
parentaecbe7a988265c0621a118368d7c189b12779dd4 (diff)
downloadcoreboot-3ba64ca3d1b055d8b4f788bc1eff4d4fedc2ec24.tar.xz
soc/intel/tigerlake: Implement CHIPSET_LOCKDOWN
BUG=b:151161585 BRANCH=none TEST=build and boot ripto/volteer and check FSP logs for lockdown parameters Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I63cec8a718285f424914e426d0399ed821588dfd Reviewed-on: https://review.coreboot.org/c/coreboot/+/39710 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/tigerlake/fsp_params.c14
1 files changed, 14 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c
index 231399c676..78cfb9f004 100644
--- a/src/soc/intel/tigerlake/fsp_params.c
+++ b/src/soc/intel/tigerlake/fsp_params.c
@@ -9,6 +9,7 @@
#include <fsp/util.h>
#include <intelblocks/lpss.h>
#include <intelblocks/xdci.h>
+#include <intelpch/lockdown.h>
#include <soc/gpio_soc_defs.h>
#include <soc/intel/common/vbt.h>
#include <soc/pci_devs.h>
@@ -97,6 +98,19 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
for (i = 0; i < 8; i++)
params->IomTypeCPortPadCfg[i] = 0x09000000;
+ /* Chipset Lockdown */
+ if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT) {
+ params->PchLockDownGlobalSmi = 0;
+ params->PchLockDownBiosInterface = 0;
+ params->PchUnlockGpioPads = 1;
+ params->RtcMemoryLock = 0;
+ } else {
+ params->PchLockDownGlobalSmi = 1;
+ params->PchLockDownBiosInterface = 1;
+ params->PchUnlockGpioPads = 0;
+ params->RtcMemoryLock = 1;
+ }
+
/* USB */
for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {
params->PortUsb20Enable[i] = config->usb2_ports[i].enable;