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| author | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2016-04-20 09:33:30 -0700 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2016-04-21 07:16:06 +0200 |
| commit | 479e31e0907e273b0ca4a8ad5326b1503144637a (patch) | |
| tree | 361aea91079289d55b4300105f44ee337435af91 /src/soc | |
| parent | cc93ce79b150abf67fbb48cc405f59b213fc6301 (diff) | |
| download | coreboot-479e31e0907e273b0ca4a8ad5326b1503144637a.tar.xz | |
imgtec/pistachio: Fix memlayout ASSERT with new binutils
With binutils 2.26 our memlayout ASSERT for mirrored SRAM regions
gets confused due to the lack of parentheses grouping the expressions.
This fixes the following issue:
LINK cbfs/fallback/bootblock.debug
mipsel-elf-ld.bfd: bootblock and gram_bootblock do not match!
mipsel-elf-ld.bfd: romstage and kseg0_romstage do not match!
Change-Id: Ib406e229b8a552d9ffc4538b55ee0269bfed62a8
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14440
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/imgtec/pistachio/include/soc/memlayout.ld | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld index 9891baec5a..05042efb9f 100644 --- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld +++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld @@ -20,8 +20,8 @@ /* SRAM memory is mapped in two different locations. Define regions in both for * full overlap checking and use this to guarantee they're kept in sync. */ #define ASSERT_MIRRORED(r1, r2) \ - _ = ASSERT(_e##r1 - _##r1 == _e##r2 - _##r2 && \ - _##r1 & 0x7fffffff == _##r2 & 0x7fffffff, \ + _ = ASSERT((_e##r1 - _##r1) == (_e##r2 - _##r2) && \ + (_##r1 & 0x7fffffff) == (_##r2 & 0x7fffffff), \ STR(r1 and r2 do not match!)); SECTIONS |