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authorWim Vervoorn <wvervoorn@eltan.com>2020-05-07 13:16:32 +0200
committerPatrick Georgi <pgeorgi@google.com>2020-05-12 20:10:52 +0000
commit5819eab5a660f915e0d18dd7d948d2af2a231aa0 (patch)
treea73ed69b2ab8334b8b8394093297bf72fa22a7ee /src/soc
parent79412ed3649ab423fb2eee73f971a928108fd041 (diff)
downloadcoreboot-5819eab5a660f915e0d18dd7d948d2af2a231aa0.tar.xz
soc/intel/skylake: Add ability to set root port ASPM
The default setting of the root port ASPM configuration can be overridden from the device tree by using a non zero value. BUG=N/A TEST=tested on facebook monolith Change-Id: I85c545d5eacb10f43b94228f1caf1163028645e0 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41171 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/skylake/chip.c5
-rw-r--r--src/soc/intel/skylake/chip.h10
2 files changed, 14 insertions, 1 deletions
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index 4ad691cb2e..ce566cf7b5 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -182,8 +182,11 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
sizeof(params->PcieRpLtrEnable));
memcpy(params->PcieRpHotPlug, config->PcieRpHotPlug,
sizeof(params->PcieRpHotPlug));
- for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++)
+ for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) {
params->PcieRpMaxPayload[i] = config->PcieRpMaxPayload[i];
+ if (config->PcieRpAspm[i])
+ params->PcieRpAspm[i] = config->PcieRpAspm[i] - 1;
+ }
/*
* PcieRpClkSrcNumber UPD is set to clock source number(0-6) for
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index e279d335bd..eb6cf9d7bc 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -289,6 +289,16 @@ struct soc_intel_skylake_config {
RpMaxPayload_256,
} PcieRpMaxPayload[CONFIG_MAX_ROOT_PORTS];
+ /* PCIE RP ASPM, ASPM support for the root port */
+ enum {
+ AspmDefault,
+ AspmDisabled,
+ AspmL0s,
+ AspmL1,
+ AspmL0sL1,
+ AspmAutoConfig,
+ } PcieRpAspm[CONFIG_MAX_ROOT_PORTS];
+
/* USB related */
struct usb2_port_config usb2_ports[16];
struct usb3_port_config usb3_ports[10];