summaryrefslogtreecommitdiff
path: root/src/soc
diff options
context:
space:
mode:
authorGarrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com>2018-03-16 13:00:46 -0500
committerAaron Durbin <adurbin@chromium.org>2018-03-17 16:32:15 +0000
commit64294eb5e241afe9d93b37b31d8a6310ec8d9279 (patch)
treefc5c294f9fdb9b8a1ab821669e6263fa2e47b3d0 /src/soc
parentfd228e979c37b66111ba1405875b08182c8d993d (diff)
downloadcoreboot-64294eb5e241afe9d93b37b31d8a6310ec8d9279.tar.xz
soc/amd/stoneyridge: Call sb_spibase() early
Call sb_spibase() early so that it will set up the SPI base address. This is another step to moving AGESA calls out of the bootblock. BUG=b:74427893 BRANCH=master TEST=Build and boot Grunt. Change-Id: I665d32f3acb0046eb6abbd363735561f0372f2a0 Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25246 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/amd/stoneyridge/southbridge.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index b4dcd8f7f5..cf059a46b2 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -559,6 +559,7 @@ void bootblock_fch_early_init(void)
sb_enable_rom();
sb_lpc_port80();
sb_lpc_decode();
+ sb_spibase();
sb_acpi_mmio_decode();
enable_aoac_devices();
}