diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2013-10-29 10:57:31 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@google.com> | 2014-02-27 06:12:25 +0100 |
| commit | 67633a558a2cc55215565ee8e9079c97acc87171 (patch) | |
| tree | 258b5bea25d16e8a58ed259b8cd3ced85481637c /src/soc | |
| parent | cf6c9cc29cedfd533da8cfaa8481560bce739097 (diff) | |
| download | coreboot-67633a558a2cc55215565ee8e9079c97acc87171.tar.xz | |
baytrail: use MCRX in iosf access functions
While most registers accesses don't need the use of the MCRX
register (upper 24 bits of address) the MCRX register should
be protected. The reference code could be doing accesses to
registers that initialized the MCRX register. Thus, any access
after that should ensure the MCRX register is initialized
appropriately.
BUG=None
BRANCH=None
TEST=Verified assembly output. Also, built and booted through
depthcharge.
Change-Id: I4d6cfbe6bb1666790c69778b8f2c8baeaf015264
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174643
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/4909
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/baytrail/baytrail/iosf.h | 1 | ||||
| -rw-r--r-- | src/soc/intel/baytrail/iosf.c | 7 |
2 files changed, 8 insertions, 0 deletions
diff --git a/src/soc/intel/baytrail/baytrail/iosf.h b/src/soc/intel/baytrail/baytrail/iosf.h index 920061f706..7f0c7f5d7b 100644 --- a/src/soc/intel/baytrail/baytrail/iosf.h +++ b/src/soc/intel/baytrail/baytrail/iosf.h @@ -45,6 +45,7 @@ #define IOSF_OPCODE(x) ((x) << 24) #define IOSF_PORT(x) ((0xff & (x)) << 16) #define IOSF_REG(x) ((0xff & (x)) << 8) +#define IOSF_REG_UPPER(x) (((~0xff) & (x))) #define IOSF_BYTE_EN_0 0x10 #define IOSF_BYTE_EN_1 0x20 #define IOSF_BYTE_EN_2 0x40 diff --git a/src/soc/intel/baytrail/iosf.c b/src/soc/intel/baytrail/iosf.c index b9f1531986..b050eba5e4 100644 --- a/src/soc/intel/baytrail/iosf.c +++ b/src/soc/intel/baytrail/iosf.c @@ -47,6 +47,7 @@ uint32_t iosf_bunit_read(int reg) uint32_t cr = IOSF_OPCODE(IOSF_OP_READ_BUNIT) | IOSF_PORT(IOSF_PORT_BUNIT) | IOSF_REG(reg) | IOSF_BYTE_EN; + write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); write_iosf_reg(MCR_REG, cr); return read_iosf_reg(MDR_REG); } @@ -57,6 +58,7 @@ void iosf_bunit_write(int reg, uint32_t val) IOSF_PORT(IOSF_PORT_BUNIT) | IOSF_REG(reg) | IOSF_BYTE_EN; write_iosf_reg(MDR_REG, val); + write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); write_iosf_reg(MCR_REG, cr); } @@ -66,6 +68,7 @@ uint32_t iosf_dunit_read(int reg) IOSF_PORT(IOSF_PORT_SYSMEMC) | IOSF_REG(reg) | IOSF_BYTE_EN; + write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); write_iosf_reg(MCR_REG, cr); return read_iosf_reg(MDR_REG); } @@ -81,6 +84,7 @@ uint32_t iosf_dunit_ch1_read(int reg) IOSF_PORT(IOSF_PORT_DUNIT_CH1) | IOSF_REG(reg) | IOSF_BYTE_EN; + write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); write_iosf_reg(MCR_REG, cr); return read_iosf_reg(MDR_REG); } @@ -92,6 +96,7 @@ void iosf_dunit_write(int reg, uint32_t val) IOSF_BYTE_EN; write_iosf_reg(MDR_REG, val); + write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); write_iosf_reg(MCR_REG, cr); } @@ -101,6 +106,7 @@ uint32_t iosf_punit_read(int reg) IOSF_PORT(IOSF_PORT_PMC) | IOSF_REG(reg) | IOSF_BYTE_EN; + write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); write_iosf_reg(MCR_REG, cr); return read_iosf_reg(MDR_REG); } @@ -112,5 +118,6 @@ void iosf_punit_write(int reg, uint32_t val) IOSF_BYTE_EN; write_iosf_reg(MDR_REG, val); + write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); write_iosf_reg(MCR_REG, cr); } |