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authorBarnali Sarkar <barnali.sarkar@intel.com>2017-06-06 15:22:30 +0530
committerAaron Durbin <adurbin@chromium.org>2017-06-09 18:49:50 +0200
commit682355ab16a946dce3f989b9581196a888b17ee8 (patch)
tree0bf05cf9424f0c0eab916dbfb32f46cefcb79de2 /src/soc
parent93d5f40be51fc118a3b303f1fa515950f883f958 (diff)
downloadcoreboot-682355ab16a946dce3f989b9581196a888b17ee8.tar.xz
soc/intel/skylake: Move update microcode from cbfs to mp_ops callbacks
FIT is already loading microcode before CPU Reset. So, we need not update the microcode again in RO FW in bootblock. But we need to update in RW FW if there is any new ucode version. So, added the update microcode function in get_microcode_info callback before MP Init to make sure BSP is using the microcode from cbfs. BUG=none BRANCH=none TEST=Build and Boot poppy Change-Id: I5606563726c00974f00285acfa435cadc90a085e Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20051 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/skylake/bootblock/cpu.c3
-rw-r--r--src/soc/intel/skylake/cpu.c1
2 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/skylake/bootblock/cpu.c b/src/soc/intel/skylake/bootblock/cpu.c
index 6963b829ea..ee344efb13 100644
--- a/src/soc/intel/skylake/bootblock/cpu.c
+++ b/src/soc/intel/skylake/bootblock/cpu.c
@@ -16,7 +16,7 @@
#include <arch/io.h>
#include <console/console.h>
-#include <cpu/intel/microcode/microcode.c>
+#include <cpu/x86/msr.h>
#include <delay.h>
#include <intelblocks/fast_spi.h>
#include <reset.h>
@@ -89,7 +89,6 @@ void bootblock_cpu_init(void)
fast_spi_cache_bios_region();
/* Set flex ratio and reset if needed */
set_flex_ratio_to_tdp_nominal();
- intel_update_microcode_from_cbfs();
}
void set_max_freq(void)
diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c
index d1ed146c1b..a40aefcf4f 100644
--- a/src/soc/intel/skylake/cpu.c
+++ b/src/soc/intel/skylake/cpu.c
@@ -480,6 +480,7 @@ static void get_microcode_info(const void **microcode, int *parallel)
microcode_patch = intel_microcode_find();
*microcode = microcode_patch;
*parallel = 1;
+ intel_microcode_load_unlocked(microcode_patch);
}
static int adjust_apic_id(int index, int apic_id)