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authorVaibhav Shankar <vaibhav.shankar@intel.com>2017-11-16 17:46:48 -0800
committerMartin Roth <martinroth@google.com>2017-11-23 05:03:14 +0000
commit6fd5a79d476b54f1670d0a06227b446ab003b2a1 (patch)
tree3a5856e3f987efc081dc8a8d2d485134c189d5fd /src/soc
parentd18db73d4997b08606d5186eee58f38c400281b6 (diff)
downloadcoreboot-6fd5a79d476b54f1670d0a06227b446ab003b2a1.tar.xz
soc/intel/cannonlake: Add PM methods to power gate SD card controller
When system enters S0ix, system fails to power gate SD card controller. This patch implements PM methods to put the SD card controller in D3 during S0ix entry. TEST=Suspend and resume using 'echo freeze > /sys/power/state'. The System should not be blocked by sd card controller. Change-Id: I9a9fe14fb6cd3b76ee95c565b3359cdae1a3c445 Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com> Reviewed-on: https://review.coreboot.org/22487 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/cannonlake/acpi/scs.asl17
1 files changed, 17 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/acpi/scs.asl b/src/soc/intel/cannonlake/acpi/scs.asl
index ed695fd580..e993ddbbf9 100644
--- a/src/soc/intel/cannonlake/acpi/scs.asl
+++ b/src/soc/intel/cannonlake/acpi/scs.asl
@@ -40,5 +40,22 @@ Scope (\_SB.PCI0) {
{
Name (_ADR, 0x00140005)
+ OperationRegion (SDPC, PCI_Config, 0x00, 0x100)
+ Field (SDPC, WordAcc, NoLock, Preserve)
+ {
+ Offset(0xA2), /* Device Power Gate config */
+ , 2,
+ PGEN, 1 /* PGE - PG Enable */
+ }
+
+ Method (_PS0, 0, Serialized)
+ {
+ Store (0, PGEN) /* Disable PG */
+ }
+
+ Method (_PS3, 0, Serialized)
+ {
+ Store (1, PGEN) /* Enable PG */
+ }
} /* Device (SDXC) */
}