diff options
| author | Wim Vervoorn <wvervoorn@eltan.com> | 2020-02-03 15:20:46 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-02-17 15:30:37 +0000 |
| commit | 84400180fa098edc47c044b8bc457d85da38858a (patch) | |
| tree | a6f02a2366ba946a48088fb613be020a41f091a5 /src/soc | |
| parent | c9a717ddb01dd7f8ba0a7fb3eb622885cd3716ad (diff) | |
| download | coreboot-84400180fa098edc47c044b8bc457d85da38858a.tar.xz | |
soc/intel{cnl,icl,skl,tgl}/bootblock: Make sure DMI PCR 2770 is set
DMI PCR 2770 (LPC IO DECODE RANGES) should be identical to LPC PCI
offset 0x80. This is specified in PCH BWG par 2.5.1.5.
Add the support to make sure this PCR is always set correctly.
BUG=N/A
TEST=tested on facebook monolith.
Change-Id: I33ff2b96dea78b5ff1c7c9416cf74f67d79f265d
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38746
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/cannonlake/bootblock/pch.c | 5 | ||||
| -rw-r--r-- | src/soc/intel/icelake/bootblock/pch.c | 5 | ||||
| -rw-r--r-- | src/soc/intel/skylake/bootblock/pch.c | 6 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/bootblock/pch.c | 5 |
4 files changed, 21 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c index a6e9f9db52..e7b79a0a68 100644 --- a/src/soc/intel/cannonlake/bootblock/pch.c +++ b/src/soc/intel/cannonlake/bootblock/pch.c @@ -172,6 +172,11 @@ void pch_early_iorange_init(void) * value program in LPC PCI offset 82h. */ pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables); + /* + * Set LPC IO Decode Ranges PCR[DMI] + 2770h [15:0] to the same + * value programmed in LPC PCI offset 80h. + */ + pcr_write16(PID_DMI, PCR_DMI_LPCIOD, lpc_get_fixed_io_decode()); } /* Program generic IO Decode Range */ diff --git a/src/soc/intel/icelake/bootblock/pch.c b/src/soc/intel/icelake/bootblock/pch.c index fd2ffd2c88..b1309a45b0 100644 --- a/src/soc/intel/icelake/bootblock/pch.c +++ b/src/soc/intel/icelake/bootblock/pch.c @@ -144,6 +144,11 @@ void pch_early_iorange_init(void) * value program in ESPI PCI offset 82h. */ pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables); + /* + * Set LPC IO Decode Ranges PCR[DMI] + 2770h [15:0] to the same + * value programmed in LPC PCI offset 80h. + */ + pcr_write16(PID_DMI, PCR_DMI_LPCIOD, lpc_get_fixed_io_decode()); } /* Program generic IO Decode Range */ diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c index ddf1139aa0..7763cf0033 100644 --- a/src/soc/intel/skylake/bootblock/pch.c +++ b/src/soc/intel/skylake/bootblock/pch.c @@ -140,6 +140,12 @@ void pch_early_iorange_init(void) * value program in LPC PCI offset 82h. */ pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables); + /* + * As per PCH BWG 2.5.1.5. + * Set LPC IO Decode Ranges PCR[DMI] + 2770h [15:0] to the same + * value programmed in LPC PCI offset 80h. + */ + pcr_write16(PID_DMI, PCR_DMI_LPCIOD, lpc_get_fixed_io_decode()); } /* Program generic IO Decode Range */ diff --git a/src/soc/intel/tigerlake/bootblock/pch.c b/src/soc/intel/tigerlake/bootblock/pch.c index cd264d682c..33637e9e01 100644 --- a/src/soc/intel/tigerlake/bootblock/pch.c +++ b/src/soc/intel/tigerlake/bootblock/pch.c @@ -169,6 +169,11 @@ void pch_early_iorange_init(void) * value program in ESPI PCI offset 82h. */ pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables); + /* + * Set LPC IO Decode Ranges PCR[DMI] + 2770h [15:0] to the same + * value programmed in LPC PCI offset 80h. + */ + pcr_write16(PID_DMI, PCR_DMI_LPCIOD, lpc_get_fixed_io_decode()); } /* Program generic IO Decode Range */ |